Method and apparatus for pipelining ordered input/output...

Details Method and apparatus for pipelining ordered input/output... Method and apparatus for pipelining ordered input/output...

2006-10-17

2006-10-17

Tran, Denise (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C710S039000

Reexamination Certificate

active

07124252

ABSTRACT:
An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output bus directed to the distributed, coherent memory. An input/output coherent cache buffer receives the prefetched data and is kept coherent with the distributed, coherent memory and with other caching agents in the system.

REFERENCES:
patent: 6049847 (2000-04-01), Vogt et al.
patent: 6058461 (2000-05-01), Lewchuk et al.
patent: 6085263 (2000-07-01), Sharma et al.
patent: 6119218 (2000-09-01), Arora et al.
patent: 6581129 (2003-06-01), Buckland et al.
patent: 6718454 (2004-04-01), Ebner et al.
patent: 0847011 (1998-10-01), None

Affiliated with

Also associated with

Rating

Method and apparatus for pipelining ordered input/output... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for pipelining ordered input/output..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for pipelining ordered input/output... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3694122