Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2006-02-21
2006-02-21
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S348000, C375S358000, C375S371000, C327S141000, C370S503000, C709S248000
Reexamination Certificate
active
07003064
ABSTRACT:
In one form, apparatus for aligning clock signals includes first and second logic circuitry for receiving respective first and second clock signals. The first and second clock signals are substantially synchronized and operations of the first logic circuitry and second logic circuitry are clocked by the respective first and second clock signals. The first logic circuitry receives a third clock signal derived from the second clock signal, and by repeatedly sampling the third clock signal with the first clock signal, the first logic circuitry repeatedly detects relative phase relations of the first and third clock signals. The second logic circuitry adjusts the phase of the third clock signal responsive to an accumulation of the phase relation detecting.
REFERENCES:
patent: 5272391 (1993-12-01), Ampe et al.
patent: 2002/0034219 (2002-03-01), Agazzi
patent: 2002/0110212 (2002-08-01), Lysdal et al.
patent: 2004/0264619 (2004-12-01), Bonaccio et al.
U.S. Appl. No. 09/732,000, filed Dec. 7, 2000, Drerup et al.
Drerup Bernard Charles
Siegmund, Jr. Richard
Carwell Robert M.
Chin Stephen
England Anthony V. S.
File Erin M.
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