Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2001-06-29
2004-04-27
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S039000, C710S055000, C711S171000
Reexamination Certificate
active
06728801
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to universal serial bus (USB) environments, and more particularly to a method and apparatus to improve performance of an enhanced host controller interface (EHCI) for USB devices.
2. Description of the Related Art
In many of today's processors and systems, such as personal computer (PC) systems, there exist USB ports for connecting various USB devices. Many USB devices are frequently used by PC users. For example, USB devices may be printers, compact disc read-only memory (CD-ROM) drives, CD-ROM writer (CDRW) drives, digital versatile disc (DVD) drives, cameras, pointing devices (e.g., computer mouse), keyboards, joy-sticks, hard-drives, speakers, etc.
Different standards of USB technology have different bandwidths. For example, Universal Serial Bus Specification, revision 1.1, Sep. 23, 1998 (USB 1.1) devices are capable of operating at 12 Mbits/second (Mbps), and Universal Serial Bus Specification, revision 2.0, Apr. 27, 2000 (USB 2.0; also known as high-speed USB) devices are capable of operating at 480 Mbps. USB 2.0 defines a multiple speed-signaling environment where a single high-speed bus may support one or more USB 1.1 classic busses through a USB 2.0 hub (Transaction Translator). In this environment, system software (the Host Controller Driver) must allocate and manage the bandwidth of USB 1.1 classic busses.
The Enhanced Host Controller Interface (EHCI) specification for a Universal Serial Bus, revision 0.95, Nov. 10, 2000, describes the register-level interface for a Host Controller (HC) for USB 2.0. In the USB EHCI specification, a single data structure known as the interrupt queue head is defined. The interrupt queue head represents and manages traffic to interrupt endpoints behind a given transaction translator (TT). A timed event, known as period promotion, may consume up to 255× the typical bandwidth of interrupt queue heads. Therefore, period promotion consumes a large portion of bandwidth in a USB 2.0 system. Thus, period promotion is very costly in a USB 2.0 system in terms of bandwidth usage.
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Garney John I.
Leete Brian A.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Mai Rijui
Perveen Rehana
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