Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
1999-06-14
2002-10-15
Le, Dieu-Minh (Department: 2184)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C714S034000
Reexamination Certificate
active
06466997
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to an end node in a high performance computer system or network, such as an ATM network, and more particularly, to a method and apparatus for improving the performance level of the end node by reducing system overhead and maximizing bus bandwidth utilization.
BACKGROUND OF THE INVENTION
A large part of the cost of networking is the cost of moving data between a host computer system and a network. Under conventional approaches, systems buffer network data in host memory buffers which are sometimes chained into linked lists. Buffer chaining is typically employed in systems utilizing “scatter-gather” techniques. For example, when the host system needs to transmit a data packet stored in buffers to a network via a network interface or adapter, it makes available to the network adapter control information associated with each buffer. The control information may include, among other buffer-related information, a pointer to a buffer of data and the length of the buffer. The chain of buffers is passed to the appropriate host system protocol stack, where the chain is augmented with the appropriate headers, and subsequently, to the driver for transmission. The driver then instructs the network adapter to copy the buffer data into the network interface's local memory and transmit the packet onto the network. The adapter must then parse the linked lists in gathering the various host memory buffers associated with the packet to be transmitted and copy the buffers into the local memory. One known technique for copying the buffer data from host memory to network adapter local memory without involving the host CPU is direct memory access (DMA).
In an alternative approach, commonly referred to as “programmed I/O”, the data copying is performed by the host CPU. During a transmit operation, the host CPU reads the address of an available adapter transmit buffer, writes the available transmit buffer with packet header and application data, and then writes the associated control information into a buffer. Once the adapter transmits the packet data onto the network, the freed buffer address is placed back in the transmit buffer and is returned to the host CPU. A receive operation functions in a similar manner. Incoming packets are queued in a receive buffer. Upon receiving an interrupt, the host CPU reads the buffer address and the contents of the buffer corresponding to the address, and subsequently returns the buffer address to the adapter to be re-used.
Because the system bus must be utilized in every host-adapter operation performed by a computer system, its characteristics and utilization have a major impact on the overall performance of the system. It can be observed that, in the aforementioned system implementations, control communications as well as data transfers take the form of both read and write transactions. Because of the added latencies associated with read access times (i.e., turnaround address-to-data time), a high ratio of read transactions to write transactions can adversely impact system bus and therefore overall system performance. Bus performance is further degraded by the number of control transactions, since control transactions consume bus bandwidth, thereby reducing the bandwidth available for data movement. Both transmit and receive throughput is adversely affected by lower levels of system bus bandwidth availability and high control/data overhead; consequently, the overall throughput rate is lower. The impact of control transactions becomes even more pronounced in systems transmitting and receiving a great number of smaller packets, because of the higher control/data overhead associated with such smaller packets. Thus, it can be seen that control communications, and more specifically, control read transactions, do not make efficient use of the system bus.
Another problem encountered in high performance systems, and more specifically, those high performance systems which employ a burst mode type of system or local bus, is the inability to burst write data to a single location, such as a data FIFO. Burst mode buses, such as the PCI bus, do not allow a burst access to a single address location. Instead, the accesses must appear on the bus as separate and distinct transactions. Again, overall performance suffers.
System performance can also be adversely affected by other host-adapter interactions, such as interrupts and reporting operations. Interrupts occur when a device like a network interface signals the host to indicate that the device needs to be serviced. In a typical network interface application, the host may be interrupted for a variety of reasons. For example, the adapter may generate an interrupt and a report to the host when a data packet to be transmitted has been transferred by a DMA operation from host memory to adapter local memory. An interrupt and report may also occur when an incoming data packet has been transferred from the adapter to the host memory. The cost of such interactions can be significant. Moreover, in the case of smaller packets or cells, such as ATM raw cells, for which little data copying is done, these other interactions often represent most of the cost of sending a packet. Thus, it may be undesirable to report status and interrupt the host on a per-cell basis.
Therefore, there exists a clearly felt need in the art for a mechanism which provides for high bus bandwidth utilization and low-latency control communications between a host computer and a high performance peripheral, such as an ATM network adapter. Further, there is a need to suppress or minimize the frequency of interrupt requests and reports queued to the host system.
SUMMARY OF THE INVENTION
Accordingly, there is provided a status report frequency mitigation method and corresponding apparatus for mitigating the frequency of status report generation of raw cells during transmit operations in a network node. The network node includes host system coupled to a network by an adapter, the adapter and host system being connected via a system bus. In the host system is a host memory including tx slots for storing data awaiting transmission onto the network.
In one embodiment of the method of the invention, the method performs the step of deciding whether or not to report consumption of a tx slot corresponding to a raw cell. If the consumption of a tx slot corresponding to the raw cell is to be reported, then the method performs the step of posting the tx slot by writing a tx slot descriptor associated with the tx slot to the adapter, setting an EOP field in the tx slot descriptor to one. In response to the posting of the tx slot, a data transfer request corresponding to each portion of data to be read from the tx slot in host memory in a separate data transfer operation is created. If the data portion is the last in the tx slot, then the method determines if the EOP field in the tx slot descriptor associated with the posted transmit slot is set. If the EOP field is set to one, then the data transfer request is serviced and a status report indicating slot consumption activity is sent to the host system.
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Cheung Wing
Mizuguchi Shinichi
Roman Peter J.
Ross Theodore L.
Tanaka Koichi
Enterasys Networks Inc.
Le Dieu-Minh
Wolf Greenfield & Sacks P.C.
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