Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
1999-04-14
2003-12-02
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C713S500000, C455S114100, C375S296000
Reexamination Certificate
active
06658506
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing verifier. More particularly, it relates to a timing verifier which accurately determines delays through differential cascode voltage swing logic (DCVSL) circuit structures.
2. Discussion of the Related Art
The Elmore delay, first presented in W. C. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wide Band Amplifier”, Journal of Applied Physics, Volume 19, 55-63 (January 1948), has been used extensively as a measure of delay for RC interconnect and for MOS circuits. Given an RC tree, the Elmore delay is computed using an equation based upon the resistance and capacitance of different paths to a defined output.
Elmore delay calculations are used in timing verification of circuits. In designing circuits, it is important to rapidly identify circuit paths of concern. One method for identifying potential problems with a circuit design is by reviewing the timing of Elmore delays within the circuit. If certain circuit paths appear to have difficulties, then a circuit simulator can be used to check the path for necessary modifications. For effective verification, a timing verifier needs to identify critical circuit paths quickly. In order to do this, various models for determining Elmore delays have been created. In particular, a resistance and capacitance are used to approximate each MOS device within the circuit by a corresponding RC structure for the calculation of the Elmore delays. Algorithms have been developed to compute Elmore delays for MOS circuits. T. M. Lynn and C. A. Mead, “Signal Delay and General RC Networks”, IEEE Transaction on Computer Aided Design, Vol. CAD-3,4, 331-349 (October 1984), and D. Martin and R. C. Rumin, “Delay Prediction from Resistance-Capacitance Model of General MOS Circuits”, IEEE Transactions on Computer Aided Design and Integrated Circuits and Systems, Vol. No. 12, 7, 997-1003 (July 1993), disclose various procedures for estimating Elmore delays for MOS devices within a circuit. In such algorithms, the resistance and capacitance models used to approximate the MOS circuit are a great source of error in computing the Elmore delay. Part of the difficulty in determining such values is that the resistance and capacitance depend upon the structure of the circuit, not solely the device itself.
In determining Elmore delays for timing verification, it is important not to miss any critical paths. Therefore, timing verifiers typically have ignored the effect of the circuit itself on the determination of the resistance and capacitance used to represent each device. Rather, timing verifiers have relied upon determination of maximum and minimum capacitances and resistance models so that no critical paths are missed. This, however, results in highly inaccurate models and many false identifications of critical paths. Each critical path identified by the timing verifier must be further analyzed and verified using more accurate methods of circuit simulation. Therefore, many false identifications of critical paths result in significant time delays and additional work. Therefore, a need exists for more accurate determinations of Elmore delays within timing verifiers. The deficiencies of timing verifiers are further expanded when analyzing circuits with DCVSL structures, which function somewhat differently than other circuit structures. Current systems do not account for such structures, which results in extreme inaccuracies in timing calculations.
Several different types of delay models and algorithms are used by timing verifiers to compute maximum delays within a CMOS circuit. Delays can be precharacterized for standard structures. The delay is written as a function of the device size, load, and input transition time. Typically, these functions are derived from simulation data. When used in a timing verifier, precharacterized delays are accurate and easy to compute. However, precharacterized delays are only applicable to simple circuit designs and structures. With non-standard circuits, precharacterized delays cannot be used. A differential cascode voltage swing logic (DCVSL) circuit is nonstandard. Therefore, it is impractical to characterize all possible delays through a DCVSL.
Several different algorithms have been used within timing verifiers which calculate Elmore delays. Typically, these algorithms use models representing the capacitance and resistance of each MOS device within the circuit. The delays through the different devices are then combined. However, due to the structure of the DCVSL circuits, the delays computed using typical Elmore delay modeling have significant errors, even exceeding 70% of the actual delay values. Elmore delay models typically neglect the specific behavior of DCVSL circuits. This causes these models to underestimate the delay from a rising input to a falling output and to over estimate the delay from a rising input to a rising output.
FIG. 1
represents a structure for a DCVSL circuit. The DCVSL circuit has two channel-connected regions
1
,
2
connected together. In considering the paths in
FIG. 1
from IN_H to OUT_H, a typical Elmore delay model divides it into two parts, corresponding to each of the channel-connected regions
1
,
2
. In the first part, it computes the delays from IN_H to OUT_L. In the second part, it determines the delay from OUT_L to OUT_H. The delays calculated in the two parts are summed together to estimate the total delay. When computing the delay from IN_H to OUT_L, the voltage on the gates PH
1
and NT
3
are assumed to be rising. The typical Elmore delay model neglects the fact that the transition time at the input at PHI is different than at the input of NT3. When computing the delay from OUT_L to OUT_H, the algorithm neglects the fact that OUT_H charge through two paths to VDD. Both these facts lead to great errors in delay estimation through DCVSL circuit structures.
Circuit simulators, like SPICE, or fast circuit simulators, can also be used for timing verification. However, although they are extremely accurate, they are also extremely slow. In order to check all of the paths in the circuit with a circuit simulator would require an exorbitant amount of time.
Therefore, a need exists for a system which can accurately and quickly determine delays through DCVSL circuits.
SUMMARY OF THE INVENTION
The present invention overcomes many of the deficiencies in the prior art by providing a timing verifier which identifies DCVSL circuits and determines delays in a manner appropriate for DCVSL circuits. In particular, the present invention determines delays by estimating the discharge through each of several paths into the DCVSL circuit. Such estimates are based upon simulations which correspond to the specific structure and characteristics of the entire circuit. The delays are based upon the percentage of discharge through each of the possible discharge paths. The present invention further utilizes an improved model for generally determining Elmore delays. In particular, the improved model accounts for the DCVSL structure in estimating the charge injected by PH
1
of FIG.
1
. By combining the percentage of discharge through different paths with an accurate Elmore delay model the present invention is able to obtain accurate delays for DCVSL circuits.
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Cong, J., et al., Optimal Wiresizing Under the Distributed Elmore Delay Model, Department of Computer Science, University of California, Los Angeles, 1993, pp. 1-19.
Elmore, W., The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifier
Farrell James Arthur
Hall Dale Hayward
Nassif Nevine
Watt Gill
Cesari and McKenna LLP
Compaq Computer Corporation
Gaffin Jeffrey
Perveen Rehana
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