Method and apparatus for performing reads of related data from a

Details Method and apparatus for performing reads of related data from a Method and apparatus for performing reads of related data from a

1997-01-17

1998-09-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

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711100, 711117, 711118, 711128, 711 1, 711 3, 711204, 711205, 711137, 365 49, G06F 100

Patent

active

058026029

ABSTRACT:
Allocation circuitry for allocating entries within a set-associative cache memory is disclosed. The set-associative cache memory comprises N ways, each way having M entries and corresponding entries in each of the N ways constituting a set of entries. The allocation circuitry has a first circuit which identifies related data units by identifying a probability that the related data units may be successively read from the cache memory. A second circuit within the allocation circuitry allocates the corresponding entries in each of the ways to the related data units, so that related data units are stored in a common set of entries. Accordingly, the related data units will be simultaneously outputted from the set-associative cache memory, and are thus concurrently available for processing. The invention may find application in allocating entries of a common set in a branch prediction table (BPT) to branch prediction information for related branch instructions.

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patent: 5581719 (1996-12-01), Steely, Jr. et al.
patent: 5586294 (1996-12-01), Goodwin et al.
patent: 5651135 (1997-07-01), Hatakeyama
patent: 5652858 (1997-07-01), Okada et al.

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