Method and apparatus for performing post-placement...

Details Method and apparatus for performing post-placement... Method and apparatus for performing post-placement...

2007-10-30

2007-10-30

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10858300

ABSTRACT:
A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes synthesizing a design for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. The design for the system is restructured after placement locations for the components are determined to improve timing for the system.

REFERENCES:
patent: 6405345 (2002-06-01), Ginetti
patent: 6871336 (2005-03-01), Anderson
patent: 6973632 (2005-12-01), Brahme et al.
patent: 7076758 (2006-07-01), Srinivasan et al.
patent: 7080344 (2006-07-01), Bajuk et al.

Affiliated with

Also associated with

Rating

Method and apparatus for performing post-placement... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for performing post-placement..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for performing post-placement... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3901994