Method and apparatus for performing page mode accesses

Details Method and apparatus for performing page mode accesses Method and apparatus for performing page mode accesses

1996-03-28

1999-03-30

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

364DIG1, A06F 1200

Patent

active

058901965

ABSTRACT:
An external bus master (205) accesses a DRAM (207) using a memory controller (804) internal to a data processor (3) without the use of external multiplexers or any other external circuitry. The need for external multiplexers and even a dedicated integrated circuit pin for providing external control during external master initiated DRAM accesses is removed by the implementation of a circuit and technique for multiplexing row and column addresses of the DRAM internally within the data processor.

REFERENCES:
patent: 4989182 (1991-01-01), Mochizuki et al.
patent: 5077693 (1991-12-01), Hardee et al.
patent: 5083172 (1992-01-01), Kiyono
patent: 5193193 (1993-03-01), Iyer
patent: 5241503 (1993-08-01), Cheng
patent: 5418924 (1995-05-01), Dresser
patent: 5440711 (1995-08-01), Susimoto
patent: 5530965 (1996-06-01), Kawasaki et al.
Levy, Markus; "The Dynamics of DRAM Technology;" EDN; Jan. 5, 1995; pp. 46-56.

Affiliated with

Also associated with

Rating

Method and apparatus for performing page mode accesses does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for performing page mode accesses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for performing page mode accesses will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1225941