Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-11-05
2001-07-10
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S036000, C710S039000, C710S108000, C710S107000, C710S108000, C710S112000, C710S120000, C710S120000
Reexamination Certificate
active
06260091
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of protocols for computer system buses; particularly, the present invention relates to protocols for buses that perform deferred/out-of-order transactions.
BACKGROUND OF THE INVENTION
In a computer system, transfers between devices such as processors, memories, input/output (I/O) units and other peripherals generally occur according to a protocol. These devices are commonly referred to as agents. The protocol is a method of handshaking that occurs between the devices during a transfer which allows each device involved in the transfer to know how the other device is going to act or perform.
Typically, transfers of data and information in a computer system are performed using multiple buses. These buses may be dedicated buses between only two devices or non-dedicated buses that are used by a number of units, bus agents or devices. Moreover, buses in the system may be dedicated to transferring a specific type of information. For instance, an address bus is used to transfer addresses, while a data bus is used to transfer data.
A bus transaction normally includes a requesting device, or agent, requesting data or a completion signal from another agent on the bus. The request usually includes some number of control signals indicating the type of request accompanied by the address of the desired data or the desired device. The device which is mapped into the address space containing the requested address responds by sending a completion signal along with any data as necessary or after accepting the data.
In some computer systems, bus transactions occur in a pipelined manner. When bus transactions are pipelined, the requests from numerous bus agents are pending at the same time. This is possible due to the fact that separate data and address buses are used. In a pipelined transaction, while an address of a request is being sent on the address bus, the data or signals corresponding to a previously requested address (on the address bus) may be returned on the data bus. In certain pipelined systems, the completion responses occur in the same order as they were requested. However, in other pipelined systems, the order of the completion responses does not have to occur in the same order as their corresponding requests. This type of bus system is commonly referred to as a split transaction bus system.
In split transaction buses, a request is initiated with a fist bus transaction to one of the agents in the computer system. If the responding agent cannot provide the response to the request at this time, the response corresponding to the request may be disassociated from the request. Eventually, when the response is ready, the response with optional data is returned to the requesting agent. The requests may be tagged so that they may be identified by the requesting agent upon their return.
To accommodate split transactions, the systems require some capability of associating a response with its address (i.e., its request). One approach is to use two separate token buses and a deferred bus. When performing a request, an address is driven onto the address bus. At the same time, a token is driven on the first token bus. This token is associated with the address request. The token is received by the agent which is to respond to the address request (i.e., the responding agent). When the agent is able to respond, the responding agent drives the token on the second token bus and the appropriate response on the data bus.
Using two token buses increases the number of pins that are required to interface with the external bus. For tokens that are 8-bits in size, using two separate token buses requires an additional sixteen pins to be added to the computer system, as well as additional space allocated on the computer board for the token buses. Moreover, the pins used to support the token buses must also be added to every bus agent package in the system. An increase in the number of pins often equates to an increase in the cost of the package. Thus, the cost of integrated circuit components in the system increases. On the other hand, the increase in bandwidth due to permitting split transactions is significant due to the ability to reorder long latency transactions behind short latency transactions issued later. It is desirable to support split bus transactions without incurring all of the increased cost of modifying integrated circuit components and the increased number of pins required.
Another approach to accommodate split transactions is to use the address and data bus to pass tokens instead of two token buses. Such an approach is described in U.S. Pat. No. 5,568,620, where a token is sent on the data bus while the address is sent on the address bus during a bus request. The responding agent drives the token onto the address bus when generating the appropriate response. Another approach is to send the token on the address bus following an address, instead of using the address bus. Thereafter, the token returns on the address bus during the response. Thus, there are approaches that do not use additional token buses.
A bus is measured by its latency, bandwidth, and scalability. In a design, tradeoffs are made among these parameters, typically at the expense of one or more of the others. Split transactions affect the latency. For instance, an additional number of cycles (e.g., 6-8) need be taken when returning data for a split transaction. If a particular device already has a long latency, the overall latency of the system is even worse. If the latency is performance critical, performance degrades as use of split transactions increases in frequency. What is needed is a system that reduces the latency of the system so that a system using split cycles frequently is not penalized.
One problem associated with the approaches to split transactions without the use of token buses is that the address bus is used twice. The processor uses the address bus when it issues a bus cycle in the system and if the cycle is split. The address bus is used again by the system to return the token when the system returns the reply for the split cycle. Therefore, the more split cycles are being used, the more address bus bandwidth is dissipated. Needing more bandwidth may be disadvantageous in that the address bus may have to be operated at a higher speed, thereby making it difficult to be electrically functional in a common clock scheme.
Another problem with dissipating more address bus bandwidth is that it directly results in loss of scalability for a given frequency. For example, if a bus is designed to support four processors and if the split cycles use up address bandwidth, then the bus may only be able to support two processors.
The present invention provides a method and apparatus for implementing a bus protocol that accommodates split transactions. The bus protocol of the present invention improves the latency, bandwidth and scalability and avoids the problems discussed above.
SUMMARY OF THE INVENTION
A computer system that accommodates split bus transactions is described. The computer system of the present invention comprises a bus, a requesting agent and a responding agent. The bus includes a response bus and a data bus. The requesting agent is coupled to the bus and generates a bus operation. The responding agent is coupled to the bus and provides a deferral response onto the response bus if not ready to complete the bus operation and thereafter provides an out-of-order deferred reply when ready to complete the bus operation. The addition of one separate token bus improves concurrency and latency, as well as maximum bandwidth obtainable.
REFERENCES:
patent: 5615343 (1997-03-01), Sarangdhar et al.
patent: 6012118 (2000-01-01), Jayakumar et al.
Huang Sunny C.
Jayakumar Muthurajan
Blakely , Sokoloff, Taylor & Zafman LLP
Dharia Rupal
Intel Corporation
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