Method and apparatus for performing modular multiplication

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

06922717

ABSTRACT:
A method and apparatus for performing modular multiplication is disclosed. An apparatus in accordance with one embodiment of the present invention includes a modular multiplier including a plurality of independent computation channels, where the plurality of independent computation channels includes a first computation channel and a second computation channel, and a coupling device interposed between the first computation channel and the second computation channel to receive a control signal and to couple the first computation channel to the second computation channel in response to a receipt of the control signal.

REFERENCES:
patent: 4218582 (1980-08-01), Hellman et al.
patent: 4493048 (1985-01-01), Kung et al.
patent: 4686645 (1987-08-01), McCanny et al.
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4737926 (1988-04-01), Vo et al.
patent: 4748583 (1988-05-01), Noll
patent: 4799182 (1989-01-01), Marwood
patent: 4914617 (1990-04-01), Putrino et al.
patent: 5047975 (1991-09-01), Patti et al.
patent: 5189636 (1993-02-01), Patti et al.
patent: 5289397 (1994-02-01), Clark et al.
patent: 5327369 (1994-07-01), Ashkenazi
patent: 5623683 (1997-04-01), Pandya
patent: 5870478 (1999-02-01), Kawamura
patent: 6035317 (2000-03-01), Guy
patent: 6061706 (2000-05-01), Gai et al.
patent: 6151393 (2000-11-01), Jeong
patent: 6209016 (2001-03-01), Hobson et al.
patent: 6219815 (2001-04-01), DesJardins et al.
patent: 6240436 (2001-05-01), McGregor
patent: 6356636 (2002-03-01), Foster et al.
patent: 6625631 (2003-09-01), Ruehle
patent: 6662201 (2003-12-01), Kawamura
patent: 6732133 (2004-05-01), Ruehle
patent: 6804696 (2004-10-01), Chen et al.
Weixin et al., A systolic linear array for modular multiplication, Oct. 1996, IEEE ASIC 2nd International Conference, pp. 171-174.
Lyh et al., Design and implementation of an RSA public-key cryptosystem, 1999, IEEE, pp. I-504 to I-507.
Bajard, Jean-Claude et al., “An RNS' Montgomery Modular Multiplication Algorithm”, Abstract, Nov. 1996, pp. 1-10.
Blum, Thomas, “Modular Exponentiation on Reconfigurable Hardware”, Thesis submitted to the Faculty of the Worcester Polytechnic Institute, Apr. 8, 1999.
Koc, Cetin Kaya, “RSA Hardware Implementation”, Version 1.0, Aug. 1995, pp. 1-28.
Rivest, R.L. et al., “A Method for Obtaining Digital Signatures and Public-Key Cryptosystems”, Abstract, pp. 1-15.
Walter, C.D., Systolic Modular Multiplication, IEEE Transactions on Computers, IEEE Inc., New York, US, vol. 42, No. 3, Mar. 1, 1993, pp. 376-378.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for performing modular multiplication does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for performing modular multiplication, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for performing modular multiplication will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3404786

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.