Method and apparatus for performing logic replication in...

Details Method and apparatus for performing logic replication in... Method and apparatus for performing logic replication in...

2007-08-14

2007-08-14

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

10806617

ABSTRACT:
A method for designing a system on a target device utilizing field programmable gate arrays is disclosed. A design is synthesized for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. Components to replicate are identified in response to criticality determined from the placement locations.

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Beraudo et al., “Timing optimization of FPGA placements by logic replication”, Design Automation Conference, 2003 Proceedings, pp. 196-201, Jun. 2-6, 2003.
Mak et al., “Temporal logic replication for dynamically reconfigurable FPGA partitioning”, IEEE Transactions on □□Computer-Aided Design of Integrated Circuits and Systems, pp. 952-959, Jul. 2003.

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