Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
1998-12-30
2001-10-16
Treat, William M. (Department: 2783)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S216000, C712S213000
Reexamination Certificate
active
06304955
ABSTRACT:
The present invention relates to computer systems and more particularly to detecting hazards in the execution of instructions that use execution units which may experience different register latencies.
BACKGROUND
Computer systems, from small handheld electronic devices to medium-sized mobile and desktop systems to large servers and workstations, are becoming increasingly pervasive in our society. Computer systems typically include one or more processors. A processor manipulates and controls the flow of data in a computer by executing instructions. Increasing the speed at which instructions are executed tends to increase the computational power of the computer. Processor designers employ many different techniques to increase processor speed to create more powerful computers for consumers. One such technique is to implement a pipeline in a processor.
A pipeline is an assembly line for instructions. When an instruction is issued to a processor pipeline, the instruction is progressively processed through separate stages in the pipeline. At any given moment, the pipeline may contain many instructions, each at different stages of processing at different stages in the pipeline. In this manner, processor resources are better utilized, thereby increasing instruction execution throughput by the processor.
The execution of one instruction in a pipeline may depend on the execution of one or more previously issued instructions. If data from a first instruction in a pipeline is needed by a second instruction in the pipeline, then the unavailability of the data from the first instruction causes a delay in the execution of the second instruction. In such a case, a portion of the pipeline may need special processing, such as being halted, or stalled, until the first instruction completes execution so the resulting data can be used by the second instruction. This condition is called a hazard.
For example, consider the following set of instructions:
load X→R
1
add R
1
+R
2
→R
3
Proper execution of the add instruction depends on proper execution of the load instruction because the add instruction requires the data in register R
1
as an operand, and the load instruction must first load this data into R
1
. Unfortunately, the result of the load instruction may not be ready by the time the add instruction is ready to use it. Consequently, execution of the add instruction must be delayed until the load instruction is completed. This is known as a read after write (RAW) hazard because the add instruction must read register R
1
after the load instruction writes to register R
1
.
Now consider the following set of instructions:
load X→R
1
add R
2
+R
3
→R
1
Proper execution of the add instruction no longer depends on the load instruction because the target of the load instruction, R
1
, is not an operand of the add instruction. R
1
is, however, the target of the add instruction, and subsequent instructions that read from register R
1
expect R
1
to contain the sum of R
2
+R
3
rather than the data loaded by the load instruction. Unfortunately, the load instruction may take longer to execute than the add instruction. Consequently, execution of the add instruction may need to be delayed until the load instruction is completed so that the load instruction does not overwrite its return data in place of R
2
+R
3
in register R
1
. This is known as a write after write (WAW) hazard because the add instruction must write to register R
1
after the load instruction writes to R
1
.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, the opcode classes of producer and consumer instructions are determined. Using these opcode classes, the register latency between the producer and consumer instructions is determined, and a register status signal is sent based on the register latency.
Other features and advantages of the present invention will be apparent from the accompanying drawings and the detailed description that follows.
REFERENCES:
patent: 4287561 (1981-09-01), Liptay
patent: 5828895 (1998-10-01), Chan et al.
patent: 5835747 (1998-11-01), Trull
patent: 5933618 (1999-08-01), Tran et al.
patent: 5966544 (1999-10-01), Sager
patent: 6035389 (2000-03-01), Grochewski et al.
patent: 6101596 (2000-08-01), Tanaka et al.
patent: 6178492 (2001-01-01), Matsuo
patent: 6216234 (2001-04-01), Sager et al.
patent: 6219781 (2001-04-01), Arora
Intel Corporation
Kaplan David J.
Treat William M.
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