Method and apparatus for performing integrated circuit timing in

Details Method and apparatus for performing integrated circuit timing in Method and apparatus for performing integrated circuit timing in

1997-08-21

2000-03-21

Teska, Kevin J.

39550023, 39550034, 39550035, 3955004, G06F 1350

Patent

active

060411694

ABSTRACT:
A method, apparatus, and article of manufacture for performing timing analysis on an integrated circuit, which run a high level chip timing tool with initial RC delays for all nets of the integrated circuit; determine a list of time-critical nets from a timing report and obtain a full RC coupling network for each time-critical net; run a detailed circuit simulator on the full RC coupling network for each time-critical net to obtain actual RC delays for each time-critical net; determine a delta time for each time-critical net, based on a difference between the initial RC delay and the corresponding actual RC delay for each time-critical net; and rerun the high level chip timing tool, including the delta time for each time-critical net to obtain a timing analysis of the integrated circuit which accounts for signal to signal noise.

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