Method and apparatus for performing incremental compilation

Details Method and apparatus for performing incremental compilation Method and apparatus for performing incremental compilation

2006-03-20

2008-12-09

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07464362

ABSTRACT:
A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second partition of the system from an incremental compilation to form a combined netlist. Fitting is performed on the combined netlist.

REFERENCES:
patent: 6102964 (2000-08-01), Tse et al.
patent: 7076751 (2006-07-01), Nixon et al.
patent: 7206967 (2007-04-01), Marti et al.

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