Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-05-01
2007-05-01
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
10406650
ABSTRACT:
An apparatus for performing imprecise bus tracing in a distributed memory symmetric multiprocessor system is disclosed. The apparatus includes a bus trace macro (BTM) module that can control the snoop traffic seen by one or more of the memory controllers in the data processing system and utilize a local memory attached to the memory controller for storing trace records. After the BTM module is enabled for tracing operations, the BTM module snoops transactions on the interconnect and packs information contained within these transactions into a block of data of a size that matches the write buffers within the memory controller. In addition, the BTM module also includes a dropped record counter for counting the number of address transactions that were not converted to trace records because all the write buffers were completely full. After an occurence of the write buffers full condition, a time stamp trace record is inserted before a new trace record can be written. The time stamp trace record includes a count of the number of address transactions that were not converted to trace records.
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Dodson John Steven
Floyd Michael Stephen
Lewis Jerry Don
Morrison Gary Alan
Beausoliel Robert
Dillon & Yudell LLP
Mehrmanesh Elmira
Salys Casimer K.
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