Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-10
2005-05-10
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06892371
ABSTRACT:
Some embodiments of the invention provide a method for generating a route for a net in an integrated circuit (“IC”) layout. The method receives a previously defined route. From the received route, it generates several constraining points for specifying a geometric route that is based on a particular wiring model. The method then uses the constraining points to generate a geometric route that traverses diagonal and Manhattan directions.
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Jacques Etienne
Teig Steven
Cadence Design Systems Inc.
Levin Naum
Siek Vuthe
Stattler Johansen & Adeli LLP
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