Method and apparatus for performing frequency detection

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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375375, 327141, 327147, H03D 324

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active

055111009

ABSTRACT:
A method and apparatus for performing frequency detection in an all digital phase lock loop (10). Frequency detection is accomplished using a frequency detector (11), coupled to an digitally controlled oscillator (DCO 16). The frequency detector (11) forces phase alignment of a reference clock signal to the DCO (16) output and then counts the number the DCO (16) output pulses occurring during a reference clock period. The reference clock signal enables the DCO (16) on one signal transition and detects the presence of an oscillator counter (52) output on the same reference clock signal transition, but one reference clock period later. A synchronizer (49) is used to pass the counter (52) output to ensure no metastability. The DCO (16) is then disabled to allow frequency adjustments to occur via other circuitry.

REFERENCES:
patent: 3562661 (1971-02-01), Crumb et al.
patent: 4577163 (1986-03-01), Culp
patent: 4795985 (1989-01-01), Gailbreath, Jr.
patent: 5057794 (1991-10-01), Shih
Nienhaus et al, "A Digital Phase Lock-Loop for VLSI Telecommunications Applications," IEEE Proceedings 1989-Southeastern-pp. 1216-1220.
Walters et al, "Digital Phase-Locked Loop with Jitter Bounded", IEEE Trans. on Circuits & Systems vol. 36, No. 7, Jul. 1989, pp. 980-987.

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