Method and apparatus for performing exception processing routine

Details Method and apparatus for performing exception processing routine Method and apparatus for performing exception processing routine

1996-10-07

1999-08-17

Lim, Krisna

Electrical computers and digital processing systems: processing

Processing control

Branching

712220, 712236, 712245, G06F 938, G06F 946

Patent

active

059387629

ABSTRACT:
An information processing apparatus and method, such that when an interruption occurs in a microprocessor, an exception processing sequence control is started, a program condition of an interrupted program and an address of the interrupted program are saved in a RAM, a program address of a jump instruction is read out from an exception processing generating source and is set in a program counter, and the exception processing sequence control is stopped. Thereafter, a normal processing sequence control is started, the jump instruction is read out from a ROM, an address of an exception processing vector is calculated according to the jump instruction, the exception processing vector is read out from the ROM, a branch address of an exception processing routine indicated by the exception processing vector is set in the program counter, and an operation state of the microprocessor is branched to the exception processing routine. Thereafter, the normal processing sequence control is stopped, and the exception processing routine is performed in the exception processing sequence control.

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BABA: "Computer Architecture", Jun. 24, 1996 (see English translation and specification p. 5).
Hardware Manual for Hitachi Single Chip RISC Micro Computer, SH7032, SH7034, HD6417032, HD6477034, and HD6437034 published in Mar, 1993 (see English translation).
Programming Manual for Hitachi Single Chip RISC Micro Computer SD7000 Series, published in Sep. 1993 (see English abstract).
Hardware Manual (HD6417604) for Super H RISC engine SH7604, published by Hitachi (see English abstract).

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