Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1998-08-28
2001-04-17
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S022000, C710S023000, C710S027000, C710S028000, C709S241000, C709S241000, C709S241000, C709S236000
Reexamination Certificate
active
06219725
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to direct memory access controllers and, more particularly, to a method and apparatus for performing direct memory access transfers to and/or from non-sequentially-addressable memory locations.
DISCUSSION OF THE RELATED ART
In a conventional computer system, a significant amount of processor time is utilized transferring data between regions of memory. Such data transfers may occur between one region of memory and another, between one region of memory and an I/O device, or between one I/O device and another. Due to the principle of spatial locality, these transfers frequently involve a large quantity (e.g., bytes, words, or blocks) of data that is read from and written to regions of memory that are spatially related (e.g., located in contiguous regions of memory). To free the processor from the burden of having to perform these data transfers itself, many computer systems include a direct memory access (DMA) controller.
A DMA controller is a specialized processor that performs transfers of spatially-related data between one region of memory and another, between one region of memory and an I/O device, and between one I/O device and another without intervention by the processor, thereby freeing the processor to perform other tasks. In most computer systems, the DMA controller is external to the processor and connected to the main memory bus of the computer system through a bus adapter, and is capable of controlling the bus.
FIG. 1
depicts a functional block diagram of a conventional computer system
100
that includes a processor
110
, a DMA controller
120
, and a memory
130
that are interconnected by a bus
140
. As shown in
FIG. 1
, the memory
130
includes a number of contiguous memory locations that are organized in a sequentially-addressable manner, in either row-major order or column-major order. When organized in row-major order, successive row memory locations are adjacent in memory; when organized in column-major order, successive column memory locations are adjacent in memory.
In the illustrative example shown in
FIG. 1
, the memory locations in memory
130
are organized in row-major order from address 0x00 to address 0xFF (that is, Hexadecimal address 00 through Hexadecimal Address FF). However, it should be appreciated that in other computer systems, the memory locations in memory
130
may alternatively be organized in column-major order. Memory
130
is depicted as having a number of rows (Row
1
through Row I) defining the height of the memory region, and a number of columns (Column 1 through Column J) defining the width of the memory region. Because memory
130
is organized in row-major order, the address of the first storage location in Row I is the next addressable storage location after the last storage location in Row I-
1
.
DMA controller
120
typically includes a number of registers
122
,
124
,
126
, including a source address register
122
, a destination address register
124
, and a length register
126
that are initialized (i.e., written to) by the processor
110
for each DMA operation. For each DMA operation, the processor
110
writes a starting source memory address from which data is to be copied in source address register
122
, a starting destination memory address to which the data is to be copied in destination address register
124
, and a length (i.e., the quantity) of data to be transferred by the DMA controller
120
in the DMA operation. Depending on the computer system, the length of the data to be transferred is typically defined in terms of bytes, words, or quad-words (i.e., 64 bits).
After registers
122
,
124
and
126
are initialized by processor
110
, the processor relinquishes control of bus
140
to the DMA controller
120
to perform the data transfer. The DMA controller
120
reads data from memory
130
starting at the memory location specified in the source address register
122
and writes that data to the memory locations starting at the memory location specified in the destination address register
124
. After this transfer, DMA controller
120
reads data from the next sequential source memory location (e.g., starting source memory address+1) and writes that data to the next sequential destination memory location (e.g, starting destination memory address+1). Generally, the DMA controller
120
includes a number of internal counters (not shown) that are incremented after each transfer to point to the next source memory location to be read and the next destination memory location to be written. The DMA controller
120
continues sequentially reading data from the next sequential source memory location and writing that data to the next sequential destination memory location until the amount of data specified in the length register
126
has been transferred. Once the amount of data specified in the length register
126
has been transferred, control of bus
140
is returned to processor
110
, whereupon the DMA operation is complete. During the data transfer, the processor
110
is free to perform other tasks. As used herein, the term “DMA operation” refers to the initialization of registers
122
,
124
, and
126
by the processor
110
and the subsequent transfer of data by the DMA controller
120
.
As described above, for each DMA operation, a number of registers are initialized by the processor
110
prior to transferring data from one memory location to another. Typically, this initialization is performed by the processor
110
in a programmed I/O mode (i.e., a conventional write operation by the processor
110
) and can consume a significant amount of time (e.g., the time to perform three write operations-one for each register) when the quantity of data to be transferred is small. Because of the time involved in initializing these registers, the use of DMA controller
120
increases the performance of the computer system only when the quantity of data to be transferred from one portion of memory to another is relatively large. That is, when the time spent initializing registers
122
,
124
, and
126
and performing the DMA data transfer is less than the time it would take to perform the same transfer using conventional read and write operations by the processor
110
.
Furthermore, because registers
122
,
124
, and
126
include only the starting source address, the starting destination address, and the quantity of data to be transferred, the data that is to be transferred during the DMA operation must necessarily be organized in sequentially-addressable memory locations in both source and destination regions of memory. Although this latter requirement is met in many computer systems, other computer systems can include memory regions that are not organized in a sequentially-addressable manner. That is, even though the memory of the computer system as a whole is generally organized in a sequentially-addressable manner, regions of that memory may be allocated so that memory locations within a region are contiguous within the region, but not sequentially-addressable.
For example,
FIG. 2
illustrates a computer graphics system that includes two different regions of memory in which memory locations are contiguous within each region, but not sequentially-addressable. The graphics system
200
includes host processor
210
, bus adapter
220
, host memory
230
, graphics hardware
240
, and graphics memory
250
. The host processor
210
communicates with host memory
230
over host memory bus
260
, and the graphics hardware
240
communicates with graphics memory
250
over graphics memory bus
270
. Bus adapter
220
permits communication between devices on the host memory bus
260
and devices on the graphics memory bus
270
. One example of a bus adapter
220
that is frequently used in graphics systems is an Intel® 440BX bus adapter chip set. The graphics system
200
may also include some additional memory (not shown) that is directly connected to the host processor
210
. In the exemplary graphics system
200
shown in
FIG.
Diehl Michael R.
Hammond Maynard
Hewlett--Packard Company
Lee Thomas
Schuster Katharina
LandOfFree
Method and apparatus for performing direct memory access... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for performing direct memory access..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for performing direct memory access... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2506000