Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reissue Patent
2001-06-14
2004-01-13
Lane, Jack A. (Department: 2188)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C710S039000, C710S111000, C710S112000, C340S003500, C340S870030
Reissue Patent
active
RE038388
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of protocols for computer system buses; particularly, the present invention relates to protocols for buses that perform deferred/out-of-order transactions.
BACKGROUND OF THE INVENTION
In a computer system, transfers between devices such as processors, memories, input/output (I/O) units and other peripherals generally occur according to a protocol. These devices are commonly referred to as agents. The protocol is a method of handshaking that occurs between the devices during a transfer which allows each device involved in the transfer to know how the other device is going to act or perform.
Typically, transfers of data and information in a computer system are performed using multiple buses. These buses may be dedicated buses between only two devices or non-dedicated buses that are used by a number of units, bus agents or devices. Moreover, buses in the system may be dedicated to transferring a specific type of information. For instance, an address bus is used to transfer addresses, while a data bus is used to transfer data.
A bus transaction normally includes a requesting device, or agent, requesting data or a completion signal from another agent on the bus. The request usually includes some number of control signals indicating the type of request accompanied by the address of the desired data or the desired device. The device which is mapped into the address space containing the requested address responds by sending a completion signal along with any data as necessary.
In some computer systems, bus transactions occur in a pipelined manner. When bus transactions are pipelined, the requests from numerous bus agents are pending at the same time. This is possible due to the fact that separate data and address buses are used. In a pipelined transaction, while an address of a request is being sent on the address bus, the data or signals corresponding to a previously requested address (on the address bus) may be returned on the data bus. In certain pipelined systems, the completion responses occur in the same order as they were requested. However, in other pipelined systems, the order of the completion responses does not have to occur in the same order as their corresponding requests. This type of bus system is commonly referred to as a split transaction bus system.
In split transaction buses, a request is initiated with a first bus transaction to one of the agents in the computer system. If the responding agent cannot provide the response to the request at this time, the response corresponding to the request may be disassociated from the request. Eventually, when the response is ready, the response with optional data is returned to the requesting agent. The requests may be tagged so that they may be identified by the requesting agent upon their return.
To accommodate split transactions, the systems require some capability of associating a response with its address (i.e., its request). One approach is to use two separate token buses and a deferred bus. When performing a request, an address is driven onto the address bus. At the same time, a token is driven on the first token bus. This token is associated with the address request. The token is received by the agent which is to respond to the address request (i.e., the responding agent). When the agent is able to respond at this time, the responding agent drives the token on the second token bus and the appropriate response on the data bus.
Using two token buses increases the number of pins that are required to interface with the external bus. For tokens that are 8-bits in size, using two separate token buses requires an additional sixteen pins to be added to the computer system, as well as additional space allocated on the computer board for the token buses. Moreover, the pins used to support the token buses must also be added to every bus agent package in the system. An increase in the number of pins often equates to an increase in the cost of the package. Thus, the cost of integrated circuit components in the system increases. On the other hand, the increase in bandwidth due to permitting split transactions is significant due to the ability to reorder long latency transactions behind short latency transactions issued later. It is desirable to support split bus transactions without incurring most of the increased cost of modifying integrated circuit components and the increased number of pins required.
In the prior art, some responding agents provide a retry response in response to a request from a bus agent. The retry response indicates to the bus agent sending the request that the responding agent is not ready to respond and that the request should be tried again later. The requesting agent then polls the responding agent from time to time to identify its availability for the transfer. After giving a retry response, the responding agent may continue processing the request. When it is ready to complete the transaction, it gives a completion response to the requesting agent and terminates polling. One problem with such a scheme is that the unnecessary polling increases bus traffic. It is desirable to reduce bus traffic when providing a retry response. Note that it is also desirable to minimize cost for bus agents unable to accomodate split transactions.
The present invention provides a method and apparatus for implementing such a bus protocol. The protocol of the present invention provides a method and apparatus for accommodating split transactions without the use of separate token buses and without the increased number of pins associated with them.
SUMMARY OF THE INVENTION
A method and apparatus for performing split bus transactions in a computer system is described. The computer system includes separate data and address buses that allow bus transactions to occur in a pipelined manner. The present invention includes a method and apparatus for initiating a first bus transaction and driving a request address on the address bus. The request address is driven by a requesting device, or agent. The responding agent drives a deferral response if unable to respond at this time. The present invention also includes a method and apparatus for driving a first token by the requesting agent on the address bus associated with the request and the address. The request address is driven on a common multiplexed address bus during the first clock and the token is driven on the common multiplexed address bus during the second clock. A responding device receives the first token and may store it internally for later use when the responding device is ready to, or is capable of, satisfying the address request. Once stored, the first bus transaction has completed.
When the responding device is ready, or is capable of, satisfying the request (e.g., the data is ready, the completion signals may be sent, etc.), the responding device initiates a second bus transaction and drives a second token on the address bus. Also the responding device drives any necessary data onto the data bus which corresponds to the original address request. In one embodiment, the second token is identical to the first token. The original requesting device receives the second token and compares the second token to the first token corresponding to its original address request. Upon determining that a match exists, the requesting device receives the completion signals and receives the data, if any, from the data bus, thus completing the second bus transaction.
REFERENCES:
patent: 4181974 (1980-01-01), Lemay et al.
patent: 4481625 (1984-11-01), Roberts et al.
patent: 4488232 (1984-12-01), Swaney et al.
patent: 4841436 (1989-06-01), Asano et al.
patent: 5006982 (1991-04-01), Ebersole et al.
patent: 5197137 (1993-03-01), Kumar et al.
patent: 5235684 (1993-08-01), Becker et al.
patent: 5535340 (1996-07-01), Bell et al.
patent: 5796977 (1998-08-01), Sarangdhar et al.
patent: 0275135 (1988-01-01), None
European Search Report dated Feb. 1, 1996; App. No. G06F13/14.*
Val Popescu, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner
Lai Konrad K.
MacWilliams Peter D.
Pawlowski Stephen S.
Rhodehamel Michael W.
Sarangdhar Nitin V.
Draeger Jeffrey S.
Intel Corporation
Lane Jack A.
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