Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-09
2008-07-15
Whitmore, Stacy (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07401314
ABSTRACT:
A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes duplicating a plurality of components in response to slack values associated with connections to the components in placement locations.
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Schabas, K. et al., “Usign logic duplication to improve performance in FPGAs”, Feb. 2003, ACM, pp. 136-142.
Marquardt, A., et al., “Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density”, 1999. ACM, pp. 37-46.
Borer Terry
Brown Stephen
Malhotra Shawn
Schabas Karl
Singh Deshanand
Cho L.
Whitmore Stacy
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