Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-12-01
2001-05-01
Ray, Gopal C. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S107000, C709S241000, C370S402000
Reexamination Certificate
active
06226704
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a personal computer, and more particularly, to the bus bridge of a personal computer.
BACKGROUND OF THE INVENTION
Many programming tasks, especially those controlling intelligent peripheral devices common in PCI (Peripheral Component Interconnect) systems, require specific events to occur in a specific order. If the events generated by the program do not occur in the hardware in the order intended by the software, a peripheral device may behave in a totally unexpected way. PCI transaction ordering rules are written to give hardware the flexibility to optimize performance by rearranging certain events which do not affect device operation, yet strictly enforce the order of events that do affect device operation.
One performance optimization that PCI systems are allowed to do is the posting of memory write transactions. Posting means the transaction is captured by an intermediate agent; e.g., a bridge from one bus to another, so that the transaction completes at the source before it actually completes at the intended destination. This allows the source to proceed with the next operation while the transaction is still making its way through the system to its ultimate destination.
While posting improves system performance, it complicates event ordering. Since the source of a write transaction proceeds before the write actually reaches its destination, other events that the programmer intended to happen after the write, may happen before the write. Many of the PCI ordering rules focus on posting buffers, requiring them to be flushed to keep this situation from causing problems.
If the buffer flushing rules are not written carefully, however, deadlock may occur. The rest of the PCI transaction ordering rules prevent the system buses from deadlocking when posting buffers must be flushed.
Referring to
FIG. 1
, it illustrates a block diagram showing the architecture commonly used in conventional personal computers. The subsystems, such as processor
11
, cache
12
and system memory
14
, are connected to I/O bus
18
through a bus bridge
13
). The bus bridge
13
provides a path through which the processor
11
may directly access I/O devices
16
mapped anywhere in the memory or I/O address spaces. It also provides a path allowing I/O bus masters direct access to system memory
14
. The bus bridge
13
may optionally include functions of data buffernng/posting and arbitration of I/O bus
18
.
As far as a bus bridge is concerned, it is responsible for maintaining transaction ordering and avoiding deadlock. Maintaining transaction ordering is mainly to have a consistent view of data in a system with write posting being allowed. Since the memory write completes at the source before it actually completes at the intended destination, the master issuing this write transaction also sets the flag to indicate that the data is now valid for other masters to use. So it right be possible that a master, regardless of which bus the master resides, reads the flag and confines the data before it is actually written to the destination. The data coherence of the system is destroyed after a master reads the stale data. As for the coherency concern, it is required to obey the ordering rule that the posted data must be written to the destination before other masters observe the valid flag and read the data. In other words, the posting buffers within the bus bridge must be flushed before the bus bridge performs a read transaction.
In addition to maintaining transaction ordering, the bus bridge should also avoid deadlock situations within the bridge. Deadlock situations typically require at least a temporary suspension of system operation, if not an entire system reset. A deadlock situation arises, for example, if the bridge contains two requests, one targeting an agent on the first bus and the second targeting an agent on the second bus, and neither request can be executed until the other is satisfied. Therefore, the deadlock prevents the bridge from operating properly.
In the existing X86 PC systems, a deadlock may occur if an I/O device makes acceptance of a memory write transaction as a target contingent on the prior completion of a memory writ e transaction as a master . If the prior write transaction initiated by the I/O master is destined for L2 cache
12
/system memory
14
, two deadlock situations may present in the system. One, the bus bridge
13
does not allow the I/O master to access L2 cache
12
/system memory
14
by withholding the I/O bus
18
ownership from the requesting I/O master due to the posting buffers haven't been flushed. And then the posted transactions from the processor bus
17
to I/O bus
18
can not be executed at the destination due to the I/O device refuses to be a target while it can not perform a memory write first. The other, the bus bridge
13
can not hold the processor bus
17
because the processor bus
17
is stalled. There are two possible causes. First, the current outstanding transaction on processor bus
17
destined for I/O bus
18
is non-postable and waits for response until the transaction is completed on I/O bus
18
. According to the ordering rule mentioned above, this non-posted transaction can not be executed on I/O bus
18
unless the posting buffers are flushed. Therefore, if some write transactions originating prior to the non-posted transaction on processor bus
17
have been posted in the posting buffers, the non-posted transaction queues up after them and stalls the processor bus
17
. Second, the current outstanding transaction on processor bus
17
destined for I/O bus
18
is postable. And the processor bus
17
is stalled when the posting buffers are full such that the transaction can not be posted. As a result, the bus bridge
13
can not hold the processor bus
17
and execute the memory write requested by the I/O master, then the posted transactions in the posting buffers can not be executed on I/O bus
18
due to the I/O device
18
refuses to be a target.
In the prior X86 PC system, the I/O bus masters are allowed to access L2 cache
12
/system memory
14
only after the bus bridge
13
holds and takes over the processor bus
17
while the posting buffers are flushed. During the period of being held, the processor
11
suspends the advanced outstanding transactions temporarily. Therefore, the bus bridge
13
can not promote system performance by having the write transactions moving in the opposite directions through the bridge executed concurrently. Furthermore, some deadlock situations may occur when the specific I/O devices
16
are resided on I/O bus
18
, wherein the I/O devices
16
require making acceptance of a memory write transaction as a target contingent on the prior completion of a memory write transaction as a master.
Therefore, there is a need to provide a system which prevents the occurrence of deadlocks within the bus bridge, while at the same time performing bus transactions orderly and concurrently.
SUMMARY OF THE INVENTION
To overcome the aforementioned problems, it is an object of the present invention to provide a method and apparatus for performing bus transactions orderly and concurrently in a bus bridge, which is compliant with current personal computers.
It is another object of the present invention to provide a deadlock-free technique for supporting concurrent processing in a bus bridge compliant with highly pipelined processor bus, such as the Pentium II processor bus.
REFERENCES:
patent: 5761454 (1998-06-01), Adusumilli et al.
patent: 5768547 (1998-06-01), Ezzet
patent: 5793996 (1998-08-01), Childers et al.
patent: 5802055 (1998-09-01), Krien et al.
patent: 5878237 (1999-03-01), Olarig
Chen Michael T. H.
Lin Wen-Hsiang
Wang Wan-Kuang
Merchant & Gould P.C.
Ray Gopal C.
Silicon Integrated Systems Corporation
LandOfFree
Method and apparatus for performing bus transactions orderly... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for performing bus transactions orderly..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for performing bus transactions orderly... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2468411