Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-11-27
2007-11-27
Beausoliel, Robert W. (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
10406649
ABSTRACT:
An apparatus for performing bus tracing with scalable bandwidth in a distributed memory symmetric multiprocesssor system is disclosed. The distributed memory symmetric multiprocessor system includes multiple processing units, each coupled to a memory module. Each of the processing units includes a memory controller and a bus trace macro (BTM) module. The memory controller is coupled to an interconnect for the symmetric multiprocessor system, and the BTM module is connected between the interconnect and the memory controller via two multiplexors. A subset of the BTM modules within the symmetric multiprocessor system is enabled for performing tracing operations such that address transactions on the interconnect are divided among the subset of the BTM modules to be selectively and separately intercepted by each BTM module within the subset of the BTM modules.
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Dodson John Steven
Lewis Jerry Don
Morrison Gary Alan
Beausoliel Robert W.
Dillon & Yudell LLP
International Business Machines - Corporation
Mehrmanesh Elmira
Salys Casimer K.
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