Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-05-19
1998-06-02
Kim, Matthew M.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711 3, 711145, 711211, 711147, G06F 1202
Patent
active
057617317
ABSTRACT:
A mechanism for ensuring the accurate and timely completion of atomic transactions by multiple nodes coupled to a memory via a common interconnect in a multiprocessor system includes a plurality of nodes coupled to a bus, the plurality of nodes including memory nodes, I/O nodes, and processor nodes. The memory nodes are each apportioned into a plurality of banks and together comprise the memory. Associated with each bank is a busy signal, indicating the availability of the bank of memory for transactions. A node may issue an atomic transaction to a block of memory data through the use of READ.sub.-- BANK.sub.-- LOCK and WRITE.sub.-- BANK.sub.-- UNLOCK instructions. The node executing the atomic transaction monitors the state of the busy signals of the banks, and when the bank is available, the node issues a READ.sub.-- BANK.sub.-- LOCK instruction, which sets the busy bit to indicate the unavailability of the bank. Upon the completion of the READ.sub.-- BANK.sub.-- LOCK instruction, the node issues a WRITE.sub.-- BANK.sub.-- UNLOCK instruction. The WRITE.sub.-- BANK.sub.-- UNLOCK instruction updates memory with the modified data and the bank busy bit is set to indicate availability of the bank to other nodes on the bus.
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Fenwick David M.
Foley Denis
Van Doren Stephen R.
Digital Equipment Corporation
Fisher Arthur W.
Kim Matthew M.
Pappas Joanne N.
Ross Gary E.
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