Method and apparatus for performing a high speed binary...

Electrical computers and digital processing systems: memory – Address formation – Using table

Reexamination Certificate

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C711S202000, C711S219000

Reexamination Certificate

active

07035995

ABSTRACT:
A hardware assisted searching mechanism is provided that offloads the processor from searching operations. In a preferred embodiment, the hardware assisted searching mechanism performs a binary search of an associated 32 bit register against a binary search table that is set up by the firmware of the storage system. From this binary search table, an index into other structures stored in firmware is obtained that may be used to identify a target device. For example, when a search is to be performed due to receipt of an I/O operation, the firmware, i.e. software instructions stored in the persistent memory chip that are executed by the system processor, writes a 32 bit value to a hardware register that is used by the hardware assisted searching mechanism of the present invention. The hardware assisted searching mechanism performs a binary search of a binary search table based on the contents of the hardware register and returns an index of the entry in another hardware register. This index is then used to index into a storage device mapping structure stored in the firmware that are indexed in the same manner as the binary search table. The index provides a starting point in the storage device mapping structure and from this starting point, the logical unit number is used to identify a particular storage array and logical unit number for the destination of the I/O operation.

REFERENCES:
patent: 5463777 (1995-10-01), Bialkowski et al.
patent: 5574910 (1996-11-01), Bialkowski et al.
patent: 5796944 (1998-08-01), Hill et al.
patent: 5860079 (1999-01-01), Smith et al.
patent: 5893137 (1999-04-01), Parks et al.
patent: 6952425 (2005-10-01), Nelson
patent: 2002/0133623 (2002-09-01), Lin et al.
patent: 2003/0009453 (2003-01-01), Basso et al.
Yazdani et al., “Fast and Scalable schemes for the IP address Lookup Problem,” pp. 83-92, IEEE, Jun. 29, 2000.

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