Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Patent
1994-11-08
1998-03-24
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
711209, G06F 1204
Patent
active
057324050
ABSTRACT:
A method and apparatus for performing a cache operation in a data processing system (10). In one form, the present invention has a "block address translation cache (BATC) only mode" in which a received logical address is compared to the logical addresses stored in only one of a plurality of address translation caches, i.e. the block address translation cache (BATC) (76). The overhead associated with loading and comparing one or more other caches (78) is not incurred. If the comparison with that one cache (BATC) (76) produces a hit, that cache (BATC) (76) supplies the address that is used as the physical address. If the comparison with that one cache (BATC) (76) produces a miss, then a 1:1 mapping is used and the received logical address is used as the physical address.
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Motorola MC88200 Cache/Memory Management Unit User's Manual; 1989,1990; pp. iii through viii, 1-1 through 3-33.
Gutierrez Joseph A.
Ho Yui Kaye
Moyer William C.
Chan Eddie P.
Hill Susan C.
Motorola Inc.
Nguyen Hiep T.
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