Electrical computers and digital processing systems: processing – Processing control
Reexamination Certificate
2000-01-21
2003-12-30
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
C712S228000, C712S244000, C709S241000
Reexamination Certificate
active
06671795
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a method and apparatus for pausing execution in a processor or the like. More particularly, an embodiment of the present invention pertains to controlling the pausing of execution of one of a plurality of threads so as to give preference to another of the threads or to save power.
BACKGROUND OF THE INVENTION
As is known in the art, a processor includes a variety of sub-modules, each adapted to carry out specific tasks. In one known processor, these sub-modules include the following: an instruction cache, an instruction fetch unit for fetching appropriate instructions from the instruction cache; decode logic that decodes the instruction into a final or intermediate format, microoperation logic that converts intermediate instructions into a final format for execution; and an execution unit that executes final format instructions (either from the decode logic in some examples or from the microoperation logic in others).
Under operation of a clock, the execution unit of the processor system executes successive instructions that are presented to it. As is known in the art, an instruction may be provided to the execution unit which results in no significant task performance for the processor system. For example, in the Intel® X86 processor systems, a NOP (No Operation) instruction causes the execution unit to take no action for an “instruction cycle.” An instruction cycle as used herein is a set number of processor clock cycles that are needed for the processor to execute an instruction. In effect, the NOP instruction stalls the processor for one instruction cycle.
A limitation of the NOP instruction is that it stalls the processor for a set unit of time. Thus, using one or more NOP instructions, the processor can only be stalled for an amount of time equal to a whole number multiple of instruction cycles.
Another limitation of the NOP instruction is that the execution unit of the processor is unable to perform any other instruction execution. For example, instructions to be executed by the execution unit may be divided into two or more “threads.” Each thread is a set of instructions to achieve a given task. Thus, if one of the threads includes a NOP instruction, this instruction is executed by the execution unit and stalls the entire processor (i.e., execution of the other thread cannot be done during the execution of the NOP instruction).
In view of the above, there is a need for an improved method and apparatus for pausing processor execution that avoids these limitations.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a method of pausing execution of instructions in a thread is presented. First it is determined if a next instruction for a first thread is an instruction of a first type. If it is then instruction of the first thread are prevented from being processed for execution while instruction from a second thread can be processed for execution.
REFERENCES:
patent: 5355457 (1994-10-01), Shebanow et al.
patent: 5524247 (1996-06-01), Mizuno
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5584031 (1996-12-01), Burch et al.
patent: 5632032 (1997-05-01), Ault et al.
patent: 5784616 (1998-07-01), Horvitz
patent: 5872963 (1999-02-01), Bitar et al.
patent: 5961584 (1999-10-01), Wolf
patent: 5961639 (1999-10-01), Mallick et al.
patent: 6216220 (2001-04-01), Hwang
patent: 6493741 (2002-12-01), Emer et al.
patent: 0 655 673 (1995-05-01), None
patent: 0 827 071 (1998-03-01), None
Patent Abstracts of Japan, vol. 008, No. 233, Oct. 26, 1984 & JP 59 111526 A (Fujitsu KK), Jun. 27, 1984.
Marr Deborah T.
Rodgers Dion
Intel Corporation
Kenyon & Kenyon
Tsai Henry W. H.
LandOfFree
Method and apparatus for pausing execution in a processor or... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for pausing execution in a processor or..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for pausing execution in a processor or... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3148933