Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-05-29
2007-05-29
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S807000, C714S752000
Reexamination Certificate
active
10321030
ABSTRACT:
A method for generating a linear block code is disclosed. A message is broken up into a plurality of sets of bits. A first group of sets is processed to determine a first partial linear block code. An adjusted partial linear block code is generated from the partial linear block code. A second group of sets is processed to determine a second partial linear block code. The adjusted partial linear block code and the second partial linear block code are combined into a single value.
REFERENCES:
patent: 3064080 (1962-11-01), Rea et al.
patent: 4928280 (1990-05-01), Nielson et al.
patent: 5157671 (1992-10-01), Karplus
patent: 6209112 (2001-03-01), Stevenson
patent: 6694478 (2004-02-01), Martinian et al.
patent: 6851086 (2005-02-01), Szymanski
patent: 6920600 (2005-07-01), Litwin et al.
patent: 7020826 (2006-03-01), Litwin et al.
patent: 2001/0050622 (2001-12-01), Hewitt et al.
Altera Corporation
Cho L.
Chung Phung My
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