Method and apparatus for parallel computation of linear...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S807000, C714S752000

Reexamination Certificate

active

10321030

ABSTRACT:
A method for generating a linear block code is disclosed. A message is broken up into a plurality of sets of bits. A first group of sets is processed to determine a first partial linear block code. An adjusted partial linear block code is generated from the partial linear block code. A second group of sets is processed to determine a second partial linear block code. The adjusted partial linear block code and the second partial linear block code are combined into a single value.

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patent: 2001/0050622 (2001-12-01), Hewitt et al.

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