Method and apparatus for parallel access to consecutive TLB entr

Details Method and apparatus for parallel access to consecutive TLB entr Method and apparatus for parallel access to consecutive TLB entr

1995-08-01

1999-07-13

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711131, 36523006, G06F 1208

Patent

active

059241250

ABSTRACT:
Apparatus and method for enabling substantially simultaneous access to consecutive entries in an addressable translation memory. The addressable translation memory may be either direct mapped or multi-way set associative. An address decoder receives input address signals and generates output select signals. Each input address signal and each output select signal corresponds to one of the registers in the translation memory. The invention includes a plurality of primary select lines, each of which transmits one of the output select signals to its corresponding register. The invention also includes a plurality of secondary select lines, each of which transmits an output select signal corresponding to a particular register to a second register, the particular register and the second register storing consecutive entries in the translation memory. The particular register and the second register receive the output select signal substantially simultaneously.

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