Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-02-14
2006-02-14
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S006000, C710S306000
Reexamination Certificate
active
07000060
ABSTRACT:
A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system with multiple nodes in a transaction order queue (TOQ). Interconnect transactions are dequeued from the TOQ and scheduled for a destination node through a buffer between the TOQ and a scheduler. Interconnect transactions of the first transaction type are blocked from the scheduler until all interconnect transactions scheduled for other nodes in the computer system have completed. No interconnect transactions are dequeued from the TOQ while an interconnect transactions of the first transaction type is blocked from the scheduler. The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol.
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Hensley Ryan J.
Shah Paras A.
Hewlett--Packard Development Company, L.P.
Perveen Rehana
Stiglic Ryan
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