Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-07-19
2005-07-19
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06920625
ABSTRACT:
An apparatus and method for optimum transparent latch placement in a macro design are provided. With the apparatus and method, a tree graph data structure is generated to represent the design wherein nodes of the tree graph data structure represent macros of the design. Each node of the tree graph data structure is augmented to include a maximum latch number and a clocking domain. Any leaf nodes of the tree graph data structure that cannot have latches placed in them, but have latch placement requirements, have their latch placement requirements added to their parent node if their parent node has more than one child node. The tree graph data structure is traversed to find the most timing critical nodes with timing requirements that have not been satisfied. A most timing critical path of these paths is identified. Intermediate nodes along this path are examined to determine if there are any latch placement requirements that must be met for the nodes. If these nodes have associated latch placement requirements, the requirements are satisfied first. Then latch placement along the critical path is performed in accordance with a one or more project specific placement rules.
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Saxena et al., “The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches,” IEEE, 1999, pp. 1-6.
Burks et al, “Optimizing of Critical Path in Circuits with Level-Sensitive Latches,” IEEE, 1994, pp. 468-473.
Bailey Wayne P.
Siek Vuthe
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