Method and apparatus for optimizing transistor cell layout with

Details Method and apparatus for optimizing transistor cell layout with Method and apparatus for optimizing transistor cell layout with

1996-11-05

2000-12-19

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

H01L 2350

Patent

active

061638773

ABSTRACT:
A computer implemented method for generating a layout for a set of transistors on a semiconductor chip. The method comprises the step of folding transistors of the set whose sizes exceed a predetermined maximum size. Then a list of implicitly enumerated diffusion sharing arrangements of the transistors of the set is created. The method also comprises the step of choosing an arrangement from the list that uses the least horizontal space on the chip and generating a layout of the set of transistors on the chip according to the chosen arrangement. Embodiments of the invention generate diffusion sharing arrangements that are unique with respect to transistor folds, transistor orientations, and transistor fold interlacing arrangements.

REFERENCES:
patent: 5675501 (1997-10-01), Aoki
patent: 5701255 (1997-12-01), Fukui
patent: 5737236 (1998-04-01), Maziasz et al.
A. Gupta, S. The, P. Hayes, "XPRESS: A Cell Layout Generator with Integrated Transistor Folding", The European Design & Test Conference 1996, pp. 393-400.

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