Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-12-10
2002-07-09
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06418552
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to printed circuit board (PCB) design and, more particularly, to a method and apparatus for optimizing the trace lengths of the PCB bus, which is a globally-clocked bus, to thereby maximize the speed of the bus.
BACKGROUND OF THE INVENTION
A typical PCB comprises several electrical components, such as, for example, microprocessors, memory elements and interface components, which communicate with each other via a globally clocked bus of the PCB. When ICs are designed, the IC designer sometimes increases the lengths of certain traces, or routes, from the pads of the die of the IC to the pins of the IC in order to equalize the lengths of the traces. The traces are conductive paths that comprise the bus of the IC package. Increasing certain trace lengths ensures that the signals traveling on the traces require the same amount of time to travel from the die to their respective pins, and vice versa.
When the PCB designer designs the PCB, the PCB designer sometimes increases the lengths of certain traces of the PCB bus in order to provide all of the traces of the PCB bus with equal lengths. However, the PCB and the IC design processes are performed independent of one another. Although the PCB designer typically utilizes the timing specifications of the IC packages in designing the PCB, these specifications normally do not provide information regarding the individual trace lengths within the IC package. Therefore, the PCB designer typically adds trace lengths to the PCB bus without having knowledge about the individual trace lengths of the IC package, which may not result in the best overall optimization of the PCB bus.
FIG. 1A
is a block diagram of two different ICs
1
and
2
that are located on a PCB (not shown) and that communicate with each other via a PCB bus
3
. The bus
3
is a globally clocked bus. The ICs
1
and
2
are “different” in that they at least have different timing parameters (e.g., setup and hold times, clock-to-Q, etc.).
FIG. 1B
is a more detailed illustration of the ICs
1
and
2
and the PCB bus
3
shown in FIG.
1
A. IC
1
has a die
4
and each signal is routed from a particular location on the die
4
to one of the pins
5
. The signals are routed by traces
6
that connect the particular locations on the die to respective pins
5
. The locations at which the traces or wire bonds are connected on the die
4
typically correspond to bus drivers (not shown). The pins
5
on IC
1
are connected to IC
2
at respective pins
8
of IC
2
via traces
9
of the PCB bus
3
. The pins
8
are connected to particular locations on the die
11
of IC
2
by traces
12
of the IC
2
.
As stated above, the PCB board designer typically does not utilize information relating to the lengths of the traces
6
and
12
of the ICs
1
and
2
, respectively. Therefore, adding trace lengths to the PCB bus traces
9
in order to equalize the lengths of the traces
9
may not result in optimization of the PCB bus
3
because doing so will not necessarily equalize the pad-to-pad trace lengths, i.e., the routing distances between the locations on the die
4
at which the traces
6
are connected and the locations on the die
11
at which the traces
12
are connected.
It would be desirable to provide a method for designing a PCB that takes into account the effects of the trace lengths within the IC packages and the timing parameters of the IC packages (e.g., setup-and-hold time, clocked Q, etc.) in determining the trace lengths of the PCB bus and the locations at which the ICs are to be placed on the PCB. By taking these factors into account in designing the PCB, the optimum placement of the ICs and the optimum trace lengths of the PCB bus can be selected, thereby allowing the speed of the PCB bus to be maximized.
Accordingly, a need exists for a method and apparatus for optimizing trace lengths of the PCB bus and for optimizing placement of the ICs on the PCB to thereby enable the speed of the PCB bus to be maximized.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for selecting trace lengths for a bus of a mounting surface, such as, for example, a printed circuit board (PCB), and for selecting the relative locations of two or three ICs on the mounting surface, which will be referred to hereinafter as a PCB. The method of the present invention utilizes information relating to the trace lengths of the buses of the ICs at issue and certain timing parameters of the ICs to determine optimal trace lengths of the PCB bus and the appropriate relative locations for the ICs on the PCB. An offset is then inserted into the global clock of the PCB bus to optimize the setup margins of the ICs. Optimization of the setup margins maximizes the speed of the PCB bus. The apparatus of the present invention is a computer that performs the method of the present invention. The computer receives the information relating to the trace lengths and the timing parameters of the ICs and processes the information to determine the appropriate trace lengths of the PCB bus and the appropriate relative locations at which the ICs are to be placed on the PCB. The computer then determines the offset that is to be inserted into the global clock of the PCB bus to optimize the setup margins of the ICs.
In accordance with the preferred embodiment of the present invention, for each signal of the ICs, the combined package delays are calculated and a determination is made as to which signal corresponds to the longest combined package delay. The relative locations of the ICs are then selected such that the signal corresponding to the longest combined package delay is routed the shortest possible distance between the ICs. The pad-to-pad flight times for all of the signals are then calculated assuming that all other signals are routed the shortest possible distances between the ICs given the selected placement of the ICs. The worst case pad-to-pad flight time is then determined and the ICs are relocated such that the signal corresponding to the worst case pad-to-pad flight time is routed the shortest possible distance between the ICs. The trace lengths for all other signals are then set so that their respective pad-to-pad flight times are equal to the worst case pad-to-pad flight time. An offset is then inserted in the global clock of the PCB bus so that the setup margins of the ICs are optimized, thereby maximizing the speed of the PCB bus.
Other features and advantages of the present invention will become apparent from the following description, drawings and claims.
REFERENCES:
patent: 5467040 (1995-11-01), Nelson
patent: 6014508 (2000-01-01), Christian et al.
patent: 6167528 (2000-12-01), Arcoleo
Hewlett--Packard Company
Levin Naum B
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