Method and apparatus for optimizing the functioning of DRAM...

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C365S096000, C365S230060, C365S203000

Reexamination Certificate

active

07072233

ABSTRACT:
In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration. Then information on the modified default time duration or on the ascertained real time duration are stored in the memory element during the test operation mode, wherein the second operation is executed offset by the modified default time duration after the execution instant of the first operation during the normal operation mode.

REFERENCES:
patent: 4575815 (1986-03-01), Delahunt
patent: 4669082 (1987-05-01), Tilghman et al.
patent: 5357471 (1994-10-01), Alapat
patent: 5946248 (1999-08-01), Chien et al.
patent: 2002/0048191 (2002-04-01), Ikehashi et al.
patent: 33 33 862 (1984-04-01), None

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