Method and apparatus for optimizing strobe to clock...

Details Method and apparatus for optimizing strobe to clock... Method and apparatus for optimizing strobe to clock...

2007-12-11

2007-12-11

Pham, Lý Duy (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050, C365S233100, C365S233500, C711S105000

Reexamination Certificate

active

11001554

ABSTRACT:
To allow a memory controller to synchronize strobe to clock relationship for a DRAM, a register, such as, a flip flop, is incorporated within the DRAM to facilitate the sampling of SCLK with DQS. Likewise, while the DRAM is in a test mode of operation, the memory controller advances or retards the clock to DQS at the memory controller hub (MCH) to achieve the proper DRAM relationship. In one embodiment, the memory controller advances DQS if a binary zero value is read. In contrast, the memory controller retards DQS if a binary one value is read.

REFERENCES:
patent: 5289580 (1994-02-01), Latif et al.
patent: 6208583 (2001-03-01), Fujiwara
patent: 6646929 (2003-11-01), Moss et al.
patent: 2003/0021164 (2003-01-01), Yoo et al.
patent: 2004/0233773 (2004-11-01), Shin
patent: 2005/0254337 (2005-11-01), Lee et al.
patent: 2001035850 (2001-05-01), None

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