Method and apparatus for optimizing performance in a...

Details Method and apparatus for optimizing performance in a... Method and apparatus for optimizing performance in a...

2006-11-28

2006-11-28

Thomson, William (Department: 2194)

Electrical computers and digital processing systems: virtual mac

Task management or control

Process scheduling

C718S103000, C718S106000, C719S318000

Reexamination Certificate

active

07143412

ABSTRACT:
A technique for improving performance in a multi-processor system by reducing access latency by correlating processor, node and memory allocation. Specifically, a Process/Thread Scheduler is modified such that system mapping and node proximity tables may be referenced to help determine processor assignments for ready-to-run processes/threads. Processors are chosen to minimize access latency. Further, the Page Fault Handler is modified such that free memory pages are assigned to a process based partially on the proximity of the memory with respect to the processor requesting memory allocation.

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