Method and apparatus for optimizing memory performance with oppo

Details Method and apparatus for optimizing memory performance with oppo Method and apparatus for optimizing memory performance with oppo

1999-12-16

2000-11-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Data refresh

365236, G11C 700

Patent

active

061479217

ABSTRACT:
A memory controller for a dynamic random access memory having counters for each chip select in the memory. The counters are incremented at a fixed interval. Programmable threshold values are provided which, when compared with the counters, indicate to the memory controller when a refresh should be opportunistically attempted and when a refresh is urgently required. The memory controller then either attempts to find an idle cycle to send the opportunistic refresh or blocks memory accesses to create a window for an urgently needed refresh. Once a refresh is sent to the memory, the appropriate counter is decremented accordingly.

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Micron Technology, Inc., Synchronous DRAM Data Sheet, 16Mb: .times.16 SDRAM.
Micron Technology, Inc., Synchronous DRAM Data Sheet, 64Mb: .times.4, .times.8, .times.16 SDRAM.
Micron Technology, Inc., Synchronous DRAM Data Sheet, 64Mb: .times.32 SDRAM.
Micron Technology, Inc., Synchronous DRAM Data Sheet, 128 MEG: .times.4, .times.8, .times.16 SDRAM.
Micron Technology, Inc., Synchronous DRAM Data Sheet, 256Mb: .times.4, .times.8, .times.16 SDRAM.

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