Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-04-01
2008-08-12
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07412670
ABSTRACT:
Methods and apparatuses for optimizing distributed multiplexed bus interconnects are described. Parameters of components that make up a distributed multiplexed bus interconnect may be optimized, such as an amount of area on a chip occupied by the component, an amount of power consumed by the component, etc., while satisfying existing timing constraints between nodes of a distributed multiplexed bus interconnect.
REFERENCES:
patent: 4641247 (1987-02-01), Laygesen et al.
patent: 4685104 (1987-08-01), Johnson et al.
patent: 4799216 (1989-01-01), Johnson et al.
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 5577023 (1996-11-01), Marum et al.
patent: 5615126 (1997-03-01), Deeley et al.
patent: 5625563 (1997-04-01), Rostoker et al.
patent: 5627480 (1997-05-01), Young et al.
patent: 5724250 (1998-03-01), Kerzman et al.
patent: 5726903 (1998-03-01), Kerzman et al.
patent: 5732246 (1998-03-01), Gould et al.
patent: 5761483 (1998-06-01), Trimberger
patent: 5847580 (1998-12-01), Bapat et al.
patent: 5850537 (1998-12-01), Selvidge et al.
patent: 5936424 (1999-08-01), Young et al.
patent: 5948089 (1999-09-01), Wingard et al.
patent: 6067650 (2000-05-01), Beausang et al.
patent: 6182183 (2001-01-01), Wingard et al.
patent: 6272668 (2001-08-01), Teene
patent: 6330225 (2001-12-01), Weber et al.
patent: 6360356 (2002-03-01), Eng
patent: 6487705 (2002-11-01), Roethig et al.
patent: 6523156 (2003-02-01), Cirit
patent: 6665851 (2003-12-01), Donelly et al.
patent: 6678645 (2004-01-01), Rajsuman et al.
patent: 6683474 (2004-01-01), Ebert et al.
patent: 6701289 (2004-03-01), Garnett et al.
patent: 6721924 (2004-04-01), Patra et al.
patent: 6772399 (2004-08-01), Saluja et al.
patent: 6880133 (2005-04-01), Meyer et al.
patent: 6910200 (2005-06-01), Aubel et al.
patent: 6910202 (2005-06-01), Minami et al.
patent: 7039881 (2006-05-01), Regan
patent: 7055121 (2006-05-01), Bolander et al.
patent: 00/22961 (2000-05-01), None
T. Minerd,Time Division Multiplexed Bus for Machine Control, IEEE Industry Applications Magazine, pp. 50-56, May/Jun. 1997, (7 pages).
P. G. Paulin et al.,A Multi-paradigm Approach to Automatic Data Path Synthesis, 23rdDesign Automation Conference, pp. 587-594, Jun. 1988, (8 pages).
K. Choi et al.,A Flexible Datapath Allocation Method for Architectural Synthesis, ACM Transactions on Design Automation of Electronic Systems, vol. 4, No. 4, pp. 376-404, Oct. 1999, (29 pages).
U.S. Appl. No. 09/634,045, filed Aug. 2, 2000, Wingard et al.
Supplementary European Search Report, EP 03726871, mailed Mar. 6, 2008, 4 pp.
Wingard D Ed-Institute of Electrical and Electronics Engineers/Association For Computing Machinery: “Micronetwork-based integration for SOCs” Proceedings of the 38TH. Annual Design Automation Conference. (DAC). Las Vegas, NV, Jun. 18-22, 2001, Proceedings of the Design Automation Conference, New York, NY: ACM, US, vol. Conf. 38, Jun. 18, 2001, pp. 673-677, XP010552471 ISBN: 1-58113-297-2 abstract; p. 673, right column, last paragraph-p. 674, left column, second paragraph; section 3.5.
Wingard D et al: “Integration Architecture For System-On-A-Chip Design” Proceedings of the IEEE 1998 Custom Integrated Circuits Conference. CICC '98. Santa Clara, CA, May 11-14, 1998, Annual Custom Integrated Circuits Conference, New York, NY: IEEE, US, vol. Conf. 20, May 11, 1998, pp. 85-88, XP000900331 ISBN: 0-7803-4293-3 abstract; p. 86, right column, first paragraph; p. 87, right column, last paragraph; p. 88, left column, second paragraph; p. 88, right column, lines 3-11.
Guerrier P et al: “A Generic Architecture for On—Chip Packet—Switched Interconnections” ACM, Mar. 27, 2000, pp. 250-256, XP01377472 abstract; section 1; p. 252, left column, second paragraph; table 3, right column.
Ho R et al: “The future of wires” Proceedings of the IEEE IEEE USA, vol. 89, No. 4, Apr. 2001, pp. 490-504, XP002469158 ISSN: 0018-9219 abstract; p. 495, right column, second and third paragraph; p. 495, right column, last line—p. 496, left column, last but one paragraph; p. 501, left column, lines 12-13.
Michael Keating, Pierre-Bricaud: “Reuse Methodology Manual for System—on—a—Chip Designs” Kluwer Academic Publishers, Second Edition, 2000, p. 28-43, 115-123, 206-228, XP002469762* the whole document.
Evans Scott C.
Meyer Michael Jude
Synek Kamil
Dinh Paul
Rutan & Tucker LLP
Sandoval Patrick
Sonics, Inc.
LandOfFree
Method and apparatus for optimizing distributed multiplexed... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for optimizing distributed multiplexed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for optimizing distributed multiplexed... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4013233