Method and apparatus for optimizing delay paths through...

Details Method and apparatus for optimizing delay paths through... Method and apparatus for optimizing delay paths through...

2007-07-24

2007-07-24

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10918974

ABSTRACT:
A method for improving a design on a field programmable gate array (FPGA) includes modifying the design in response to a unate characteristic of an input to a node on the FPGA, and rising and falling delays of a node feeding the input.

REFERENCES:
patent: 5706473 (1998-01-01), Yu et al.
patent: 5903467 (1999-05-01), Puri et al.
patent: 6292916 (2001-09-01), Abramovici et al.
patent: 6327557 (2001-12-01), Croix
patent: 2002/0178432 (2002-11-01), Kim et al.

Affiliated with

Also associated with

Rating

Method and apparatus for optimizing delay paths through... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for optimizing delay paths through..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for optimizing delay paths through... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3729763