Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2005-08-23
2005-08-23
Browne, Lynne H. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S500000, C703S019000
Reexamination Certificate
active
06934872
ABSTRACT:
A method and apparatus for optimizing clock distribution in a circuit to reduce the effect of power supply noise. Parameters are determined including: a response curve of a power source for a circuit, a delay sensitivity of a clock net in the circuit to the power source, a delay sensitivity of a data net in the circuit to the power source, a data delay for the data net, and a clock delay for the clock net. The clock delay is adjusted to reduce the effect of power supply noise on the data net. The adjusting is based on the response curve of the power source, the delay sensitivity of the clock net, the delay sensitivity of the data net, the data delay, and the clock delay. The adjusting includes adding a pre-distribution clock delay.
REFERENCES:
patent: 5313501 (1994-05-01), Thacker
patent: 5627736 (1997-05-01), Taylor
patent: 6075832 (2000-06-01), Geannopoulos et al.
Barkatullah Javed
Burton Edward A.
Ma Hung-Piao
Rahal-Arabi Tawfik M.
Wong Keng L.
Blakely , Sokoloff, Taylor & Zafman LLP
Browne Lynne H.
Henry Matthew
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