Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-03
2010-06-29
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07747974
ABSTRACT:
A method and apparatus for optimizing body bias connections to NFETs and PFETs using a deep n-well grid structure. A deep n-well is formed below the surface of a CMOS substrate supporting a plurality of NFETs and PFETs having a nominal gate length of less than 0.2 microns. The deep n-well is a grid structure with a regular array of apertures providing electrical continuity between the bottom of the substrate and the NFETs. The PFETs reside in surface n-wells that are continuous with the buried n-well grid structure. The grid and n-well layout is performed on the basis of the functionality of the PFETs contained in the n-wells.
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Burr James B.
Schnaitter William N.
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