Method and apparatus for non-volatile multi-bit memory

Details Method and apparatus for non-volatile multi-bit memory Method and apparatus for non-volatile multi-bit memory

2006-10-23

2009-11-10

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Systems using particular element

Resistive

C365S163000

Reexamination Certificate

active

07616472

ABSTRACT:
A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.

REFERENCES:
patent: 5687112 (1997-11-01), Ovshinsky
patent: 5789277 (1998-08-01), Zahorik et al.
patent: 6150253 (2000-11-01), Doan et al.
patent: 7161167 (2007-01-01), Johnson
patent: 7254059 (2007-08-01), Li et al.
patent: 7485891 (2009-02-01), Hamann et al.
patent: 2007/0108431 (2007-05-01), Chen et al.
patent: 2008/0135824 (2008-06-01), Lai et al.

Affiliated with

Also associated with

Rating

Method and apparatus for non-volatile multi-bit memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for non-volatile multi-bit memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for non-volatile multi-bit memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4103069