Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2003-03-13
2004-06-08
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S031000, C326S034000, C326S082000, C326S083000, C326S086000
Reexamination Certificate
active
06747476
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to termination circuits and methods therefor. More particularly, the present invention relates to termination circuits that provide fast and efficient clamping for signals transmitted via transmission lines in electronic systems.
2. Description of Relevant Art
In the design and implementation of electronic systems (such as digital computers, consumer/commercial electronic devices, or the like), particularly those employing integrated circuits, undesired transmission line effects are of a particular concern. As signals travel down transmission lines, e.g., traces on a printed circuit board, reflections may occur on the lines. The reflections are due to, for example, mismatched impedances between the receiver circuit and the line, which may cause the signal to reflect back and forth, giving rise to ringing. These reflections and other undesired transmission lines effect are exacerbated as the operating speed of the signal increases. If left uncorrected, the reflections may cause the signal's voltage to swing outside of the defined “0” or “1” voltage levels, thereby causing the receiving device to incorrectly interpret the signal received and generate erroneous results.
To address this problem, a variety of techniques have been tried in the prior art. One such technique is shown in
FIG. 1
illustrating a termination circuit
100
includes a top active clamping device
102
and a bottom active clamping device
104
. In the circuit
100
, the top active clamping device
102
is implemented by a p-channel MOS device
132
and serves to clamp the signal on a transmission line
106
at about a second reference voltage (e.g., V
DD
). On the other hand, bottom active clamping device
104
is implemented by an n-channel MOS device
120
and serves to clamp the signal on transmission line
106
at a first reference voltage (e.g., ground or GND). In accordance with the convention utilized herein, the top devices are employed to clamp the voltage level of the signal on the transmission line at its upper range (e.g., to about V
DD
), while the bottom devices are employed to clamp the voltage level of the signal at its lower range (e.g., to about ground).
The source of MOS device
132
can be coupled to V
DD
while the source of MOS device
120
can be coupled to ground. The drains of devices
132
and
120
are both coupled to transmission line
106
as shown. Referring now to bottom active clamping device
104
, a gate
114
of MOS device
120
is coupled to both the gate and drain of a bottom threshold reference device
113
having an input impedance r
1
. As shown in
FIG. 1
, bottom threshold reference device
113
includes an n-channel MOS device
118
, which is arranged in a gate-to-drain connected configuration.
When sufficient current flows into the drain of n-channel MOS device
118
the current may be sourced from any conventional current sourcing arrangement, which is shown symbolically by current source
116
in FIG.
1
), gate
114
of bottom active clamping device
104
is biased at about one threshold voltage V
T
of n-channel MOS device
118
above ground. Typically, the voltage at gate
114
is biased at the threshold voltage V
T
of n-channel MOS device
118
plus a small amount of overdrive voltage necessary to sustain the current through device
118
.
When the signal on transmission line
106
begins to reflect and dips below ground, i.e., as soon as the potential difference between the gate of n-channel MOS device
120
of bottom active clamping device
104
and its source exceeds V
T
, n-channel device
120
begins to conduct to source current from its drain, which is connected to ground as shown in FIG.
1
. Accordingly, the signal is clamped at about or slightly below ground. As noted, gate
114
of n-channel device
120
is typically biased slightly above V
T
. Consequently, it is typically the case that n-channel device
120
begins to conduct when the signal on transmission line
106
is slightly above ground (e.g., perhaps 0.1 V above ground). In this manner, n-channel device
120
would be in full conduction when the signal on transmission line
106
dips below ground.
A similar arrangement exists with reference to gate
130
of the p-channel MOS device
132
of top active clamping device
102
in that the gate
130
of MOS device
132
is coupled to both the gate and drain of a top threshold reference device
111
having an input impedance r
2
. More particularly, the gate
130
is coupled to the gate and drain of p-channel MOS device
134
. The source of p-channel MOS device
130
is coupled to V
DD
as shown. When sufficient current flows out of the drain of p-channel device
134
, gate
130
of p-channel device
132
is biased at about V
DD
-V
T
, where V
T
is the threshold voltage of p-channel MOS device
134
. Actually, gate
130
of p-channel device
132
is biased slightly below this value (V
DD
-V
T
) due to the presence of the overdrive voltage necessary to sustain current through p-channel MOS device
134
.
When the signal on transmission line
106
begins to reflect and rises above V
DD
, p-channel MOS device
132
turns on to clamp this signal at about V
DD
. Due to the presence of the aforementioned overdrive voltage, p-channel MOS device
132
typically turns on slightly before the voltage level of the signal on transmission line
106
reaches V
DD
, thereby ensuring that p-channel MOS device
132
is fully turned on when the signal's voltage level exceeds V
DD
.
As well known in the art, all junction type devices (including transistors) have intrinsic capacitance loading between the various junctions commonly referred to as parasitic capacitance. One such parasitic component particularly relevant to the inventive termination circuit are referred to as MOSFET capacitances. These parasitic components are mainly responsible for the intrinsic delay of logic gates.
FIG. 2
illustrates a typical MOSFET
200
having associated junction parasitic capacitances represented as lumped elements between the device terminals. Based on their physical origins, the parasitic device capacitances can be classified into two major groups: (1) oxide-related capacitances and (2) junction capacitances. In the example shown, the gate-oxide-related capacitances are Cgd (gate-to-drain capacitance), Cgs (gate-to-source capacitance), and Cgb (gate-to-substrate capacitance). It is well known in the art that the gate-to-channel capacitance is distributed and voltage dependent, and consequently, all of the oxide-related capacitances described here changes with the bias conditions of the transistor. Note that the total gate oxide capacitance is mainly determined by the parallel-plate capacitance between the gate and the underlying structures. Hence, the magnitude of the oxide-related capacitances is very closely related to (1) the gate oxide thickness, and (2) the area of the MOSFET gate.
Referring back to
FIG. 1
, the gate to drain parasitic capacitance C
gd1
(associated with transistor
132
) and C
gd2
(associated with transistor
120
) degrade the clamping performance of the termination circuit
100
by causing the gate voltages of the clamping transistors
132
and
120
to vary in relation to the input voltage rise or fall on the transmission line
106
. In some cases, this variation in gate voltage can be hundreds of millivolts.
In addition to the presence of the parasitic capacitances C
gd1
and C
gd2
that degrade the clamping performance of the termination circuit
100
, DC power in excess of that required by the current source
116
is dissipated due to what is referred to as the short channel effect. Currents I
p
and I
n
are always flowing in the bias voltage generator circuits
111
and
113
, respectively. However currents that may be an order of magnitude greater than bias currents I
p
and I
n
can flow in the clamping transistors when there exists both a voltage between the source and drain of greater than a threshold voltage, and also a voltage between the source
California Micro Devices
Eakin James E.
Nguyen Khai
Tokar Michael
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