Method and apparatus for non-concurrent arbitration of multiple

Details Method and apparatus for non-concurrent arbitration of multiple Method and apparatus for non-concurrent arbitration of multiple

1999-08-23

2000-12-19

Etienne, Ario

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710110, 710128, 710129, 710240, G06F 1300

Patent

active

061638269

ABSTRACT:
A processor-based system such as a microcontroller supports a non-concurrent mode in which a bus master requesting ownership of a peripheral bus is forced to acquire ownership of both the peripheral bus and a processor bus. The system includes a peripheral bus arbiter to detect a peripheral bus request for the peripheral bus by a bus master, to generate a processor bus request for the processor bus in response to detecting the peripheral bus request, and to grant the bus master ownership of the peripheral bus if the bus master is granted ownership of the processor bus. The peripheral bus arbiter maintains ownership of the processor bus by the bus master until the bus master releases ownership of the peripheral bus. Similarly, a bus master seeking ownership of the processor bus can be forced to acquire ownership of the peripheral bus. The non-concurrent mode can be applied to various multi-bus architectures. One advantage of the non-concurrent mode is improved debug capability.

REFERENCES:
patent: 5418914 (1995-05-01), Heil et al.
patent: 5619661 (1997-04-01), Crews et al.
PCI System Architecture, Fourth Edition, Copyright .COPYRGT.1999, by Mindshare, Inc., title page and pp. 649-671.

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