Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-08-15
2006-08-15
Portka, Gary (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S204000, C711S213000
Reexamination Certificate
active
07093077
ABSTRACT:
A method and apparatus for issuing one or more next-line prefetch requests from a predicted memory address. The first issued next-line prefetch request corresponds to a cache line having a memory address contiguous with the predicted memory address. Any subsequent next-line prefetch request corresponds to a cache line having a memory address contiguous with a memory address associated with a preceding next-line prefetch request.
REFERENCES:
patent: 4980823 (1990-12-01), Liu
patent: 5317718 (1994-05-01), Jouppi
patent: 5357618 (1994-10-01), Mirza et al.
patent: 5423014 (1995-06-01), Hinton et al.
patent: 5500948 (1996-03-01), Hinton et al.
patent: 5664147 (1997-09-01), Mayfield
patent: 5666505 (1997-09-01), Bailey
patent: 5694568 (1997-12-01), Harrison, III et al.
patent: 5701448 (1997-12-01), White
patent: 5724422 (1998-03-01), Shang et al.
patent: 5740399 (1998-04-01), Mayfield et al.
patent: 5752037 (1998-05-01), Gornish et al.
patent: 5758119 (1998-05-01), Mayfield et al.
patent: 5764946 (1998-06-01), Tran et al.
patent: 5765214 (1998-06-01), Sywyk
patent: 5778423 (1998-07-01), Sites et al.
patent: 5991848 (1999-11-01), Koh
patent: 6012135 (2000-01-01), Leedom et al.
patent: 6055622 (2000-04-01), Spillinger
patent: 6076151 (2000-06-01), Meier
patent: 6079005 (2000-06-01), Witt et al.
patent: 6081479 (2000-06-01), Ji et al.
patent: 6085291 (2000-07-01), Hicks et al.
patent: 6092186 (2000-07-01), Betker et al.
patent: 6098154 (2000-08-01), Lopez-Aguado et al.
patent: 6119221 (2000-09-01), Zaiki et al.
patent: 6131145 (2000-10-01), Matsubara et al.
patent: 6138212 (2000-10-01), Chiacchia et al.
patent: 6161166 (2000-12-01), Doing et al.
patent: 6212603 (2001-04-01), McInerney et al.
patent: 6247107 (2001-06-01), Christie
patent: 6275918 (2001-08-01), Burky et al.
patent: 6292871 (2001-09-01), Fuente
patent: 6295594 (2001-09-01), Meier
patent: 1150213 (2001-10-01), None
Steven P. Vanderwiel et al, “Data Prefetch Mechanisms,” ACM Computing Surveys, vol. 32, No. 2, Jun. 2000, pp. 174-199.
Cooksey, et al., “Content-Based Prefetching: Initial Results”, presented at 2nd workshop on Intelligent Memory Systems (IMS00), Nov. 2000, pp. 1-17.
Roth, et al., “Dependence Based Prefetching for Linked Data Structures”, In the proceedings of the 8th International Conference on Architectural Support of Programming Languages and Operating Systems, Oct. 1998, pp. 115-126.
Boehm, “Hardware and Operating System Support for Conservative Garbage Collection”, Xerox PARC, Palo Alto, CA, 1991 IEEE, pp. 61-67.
Charney, et al., “Generalized Correlation-Based Hardware Prefetching”, School of Electrical Engineering, Cornell University, Ithaca, NY, Technical Report No. EE-CEG-95-1, Feb. 13, 1995, pp. 1-45.
Chen, et al., “Reducing Memory Latency via Non-Blocking and Prefetching Caches”, Department of Computer Science and Engineering, University of Washington, Seattle, WA, 1992, pp. 51-61.
Joseph, et al., “Prefetching Using Markov Predictors”, IBM T.J. Watson Research Lab, Yorktown Heights, NY, 1997, pp. 252-263.
Jouppi, “Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers”, Digital Equipment Corporation Western Research Lab, Palo Alto, CA, 1990 IEEE, pp. 364-373.
Lipasti, et al., “SPAID: Software Prefetching in Pointer-and Call-Intensive Environments”, IBM Corporation, Rochester, MN, 1995 IEEE, pp. 231-236.
Luk, et al., “Compiler-Based Prefetching for Recursive Data Structures”, Department of Computer Science, Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada, 1996, pp. 222-233.
Mowry, et al., “Design and Evaluation of a Compiler Algorithm for Prefetchng”, Computer Systems Laboratory, Standford University, CA, 1992, pp. 62-73.
Ozawa, et al., “Cache Miss Heuristics and Preloading Techniques for General-Purpose Programs”, Fujitsu Laboratories Ltd., Kawasaki, Japan, 1995 IEEE, pp. 243-248.
Palacharla, et al., “Evaluating Stream Buffers as a Secondary Cache Replacement”, Computer Sciences Department, University of Wisconsin, Madison, WI, 1994 IEEE, pp. 24-33.
Yang, et al., “Push vs. Pull: Data Movement for Linked Data Structures”, Department Computer Science, Duke University, Durham, NC, 2000, pp. 176-186.
Patterson et. al.,Computer Architecture A Quantitative Approach, Second Edition, Published 1996, pp. 1-5.
Tanenbaum et. al., Structured Computer Organization, Fouth Edition, Published 1999, pp. 1-3.
Cooksey Robert N.
Jourdan Stephan J.
Chery Mardochee
Intel Corporation
Portka Gary
Tweet Kerry D.
LandOfFree
Method and apparatus for next-line prefetching from a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for next-line prefetching from a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for next-line prefetching from a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3668354