Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-03-13
2001-06-05
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06243849
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to the field of semiconductor design and fabrication. Specifically, this invention relates to the technique of filtering of netlist to facilitate the placement of particular cells on an integrated circuit chip.
2. Description of the Related Art
Cell placement in semiconductor fabrication involves determining placement of particular cells on the surface of a integrated circuit device. As is described more fully below, there are different types of cells to be placed, including core cells (such as logic cells), I/O cells (input/output cells) and scan cells. Some cell placement systems place different cells at different stages of the design process. For example, I/O cells are generally placed at the periphery of the integrated circuit device and can be placed before the core cells are placed in the core (middle) of the device. The purpose of the present invention is to facilitate the placement of cells where different cells are placed at different stages of the integrated circuit design process.
a. Integrated Circuit Basics
An integrated circuit chip (hereafter referred to as an “IC” or a “chip”) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. As discussed above, the cells can include core cells, scan cells and I/O cells.
A net is a set of two or more pins which must be connected, thus connecting the logic circuits having the pins. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins, that must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins. Some nets may include hundreds of pins or thousands or tens of thousands to be connected. A netlist is a list of nets including names of connected pins or a list of cells including names of nets that connect to pins of cells.
b. Chip Fabrication
As mentioned above, the present invention involves cell placement. Cell placement is one of the steps necessary for the fabrication of an IC. These additional steps are very well known by those skilled in the art of semiconductor fabrication and are briefly described below.
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
The layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator.
During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The component formation requires very exacting details about geometric patterns and separation between them. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Currently, the minimum geometric feature size of a component is on the order of 0.2 microns. However, it is expected that the feature size can be reduced to 0.1 micron within the next few years. This small feature size allows fabrication of as many as 4.5 million transistors or 1 million gates of logic on a 25 millimeter by 25 millimeter chip. This trend is expected to continue, with even smaller feature geometries and more circuit elements on an integrated circuit, and of course, larger die (or chip) sizes will allow far greater numbers of circuit elements.
Due to the large number of components and the exacting details required by the fabrication process, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance.
The objective of physical design is to determine an optimal arrangement of devices in a plane or in a three dimensional space, and an efficient interconnection or routing scheme between the devices to obtain the desired functionality.
An exemplary integrated circuit chip is illustrated in FIG.
1
and generally designated by the reference numeral
26
. The circuit
26
includes a semiconductor substrate
26
A on which are formed a number of functional circuit blocks that can have different sizes and shapes. Some are relatively large, such as a central processing unit (CPU)
27
, a read-only memory (ROM)
28
, a clock/timing unit
29
, one or more random access memories (RAM)
30
and an input/output (I/O) interface unit
31
. These blocks, commonly known as macroblocks, can be considered as modules for use in various circuit designs, and are represented as standard designs in circuit libraries.
The integrated circuit
26
further comprises a large number, which can be tens of thousands, hundreds of thousands or even millions or more of small cells
32
. Each cell
32
shown herein represents a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells that consist of two or more interconnected gates or logic elements are also available as standard modules in circuit libraries.
The cells
32
and the other elements of the circuit
26
described above are interconnected or routed in accordance with the logical design of the circuit to provide the desired functionality. Although not visible in the drawing, the various elements of the circuit
26
are interconnected by electrically conductive lines or traces that are routed, for example, through vertical channels
33
and horizontal channels
34
that run between the cells
32
.
The input to the physical design problem is a circuit diagram, and the output is the layout of the circuit. This is accomplished in several stages including partitioning, floor planning, placement, routing and compaction.
Partitioning. A chip may contain several million transistors. Layout of the entire circuit cannot be handled due to the limitation of memory space as well as the computation power available. Therefore it is normally partitioned by grouping the components into blocks such as subcircuits and modules. The actual partitioning process considers many factors such as the size of the blocks, number of blocks and number of interconnections between the blocks.
The output of partitioning is a set of blocks, along with the interconnections required between blocks. The set of interconnections required is the netlist. In large circuits, the partitioning process is often hierarchical, although non-hierarchical (e.g. flat) processes can be used, and at the topmost level a circuit can have between 5 to 25 blocks. However, greater numbers of blocks are possible and contemplated. Each block is then partitioned recursively into smaller blocks.
Floor planning and placement. This step is concerned with se
Liang Mike
Singh Virinder
Garbowski Leigh Marie
LSI Logic Corporation
Mitchell Silberberg & Knupp LLP
Smith Matthew
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