Method and apparatus for net-aware critical area extraction

Details Method and apparatus for net-aware critical area extraction Method and apparatus for net-aware critical area extraction

2007-01-24

2010-02-09

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07661080

ABSTRACT:
In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of a plurality of interconnected shapes spanning one or more layers of the integrated circuit. All generators for opens are then defined and identified. The Voronoi diagram of the identified generators is computed, and the critical area is computed in accordance with the Voronoi diagram.

REFERENCES:
patent: 6178539 (2001-01-01), Papadopoulou et al.
patent: 6247853 (2001-06-01), Papadopoulou et al.
patent: 6317859 (2001-11-01), Papadopoulou
patent: 6918101 (2005-07-01), Satya et al.
patent: 6948141 (2005-09-01), Satya et al.

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