Method and apparatus for nested control flow of instructions...

Details Method and apparatus for nested control flow of instructions... Method and apparatus for nested control flow of instructions...

2007-10-09

2007-10-09

Sparks, Donald (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Instruction modification based on condition

C712S235000, C712S233000, C712S234000

Reexamination Certificate

active

10756853

ABSTRACT:
A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction multiple data (SIMD) operations. The method and apparatus further includes a first memory device storing a plurality of instructions wherein each of the plurality of instructions includes a plurality of extra bits. The processor is operative to execute the instructions based on the extra bits and in conjunction with a context bit. The method and apparatus further includes a second memory device, such as a general purpose register operably coupled to the processor, the second memory device receiving an incrementing counter instruction upon the execution of one of the plurality of instructions. As such, the method and apparatus allows for nested control flow through a single context bit in conjunction with instructions having a plurality of extra bits.

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T. Blank, The MasPar MP-1 Architecture Proceeding of Compcon, Spring 90, The 35th IEEE Computer Society International Conference, San Franciso, CA, Feb. 1990, pp. 20-23.
Keryell, Ronan and Paris, Nicolas, Activity Counter: New Optimization for the Dynamic Scheduling of SIMD Control Flow, Jan. 1993, pp. 1-16.

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