Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2003-04-21
2004-09-21
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S037000, C326S046000
Reexamination Certificate
active
06794896
ABSTRACT:
FIELD OF THE INVENTION
One or more aspects of the invention relate generally to programmable logic devices and, more particularly, to packet processing for routing using multithreading.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device is called a field programmable gate array (FPGA).
An FPGA conventionally includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are conventionally programmed by loading a stream of configuration data (bit stream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. Additionally, an FPGA may include: embedded memory, such as block random access memories (BRAMs); one or more microprocessors, sometimes referred to as embedded cores; digital clock managers (DCMs); and low voltage differential signaling (LVDS) input/output (I/O) interfaces.
The combination of components on an FPGA may be used for system-level integration, sometimes referred to as “system-on-a-chip” (SoC). Accordingly, system-level integration with FPGAs is desirable for flexibility and efficiency.
SUMMARY OF THE INVENTION
An aspect of the invention is a method for multithread processing of a packet, comprising: initiating a packet recognition thread responsive to receiving the packet to a port; triggering a media access control (“MAC”) recognition thread responsive to the packet recognition thread; activating a network protocol recognition thread responsive to the MAC recognition thread; initiating an address lookup thread responsive to the network protocol recognition thread; and initiating a MAC write thread responsive to the network protocol recognition thread. The MAC recognition thread, the network protocol thread, the address lookup thread and the MAC write thread all may complete their respective executions prior to completion of the packet recognition thread.
An aspect of the invention is a method for multithread processing of a packet, comprising: initiating a packet recognition thread responsive to receiving the packet to a port; broadcasting an incoming data stream of the packet to ports other than the port; activating a media access control (“MAC”) recognition thread responsive to the packet recognition thread; initiating a packet encapsulation thread responsive to the MAC recognition thread; triggering a network protocol recognition thread responsive to the MAC recognition thread; determining whether or not encapsulation is to be done responsive to the network protocol recognition thread; deactivating the packet encapsulation thread responsive to the network protocol recognition thread should it be determined that encapsulation is not to be done; starting an address lookup thread responsive to the network protocol recognition thread; and starting a MAC write thread responsive to the network protocol recognition thread. The MAC recognition thread, the network protocol thread, the address lookup thread and the MAC write thread all may be completely executed prior to completion of the packet recognition thread.
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Tran Anh Q.
Webostad Eric
Xilinx , Inc.
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