Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-12-01
2001-05-08
Etienne, Ario (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
Reexamination Certificate
active
06230225
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains in general to the implementation of a computer system bus, and more particularly, but not by way of limitation, to a method and apparatus for multicasting on a computer system bus wherein information from a single bus master is broadcast to multiple targets during a single bus transaction.
BACKGROUND OF THE INVENTION
Computer systems have achieved wide usage in modem society. During operation, a computer system processes and stores data at a speed and at a level of accuracy many times that which can be performed manually. Successive generations of computer systems have permitted ever-increasing amounts of data to be processed at ever-increasing rates.
Computer systems are sometimes operated as stand-alone devices or connected together by way of network connections, typically together with a network server, to form a computer network. When networked together, communication between the separate computer systems is possible. Files and other data, stored or generated at one computer system, can be transferred to another computer system.
A conventional computer system typically includes one or more Central Processing Units (CPUs) capable of executing algorithms forming applications and a computer main memory. Peripheral devices, both those embedded together with a CPU or constructed to be separate therefrom, also typically form portions of a conventional computer system. Computer peripheral devices include, for instance, video graphics adapters, Local Area Network (LAN) interfaces, Small Computer System Interface (SCSI) bus adapters, and mass storage devices, such as disk drive assemblies.
A computer system further typically includes computer buses which permit communication of data between various portions of the computer system. For example, a host bus, a memory bus, at least one high-speed bus, a local peripheral expansion bus, and one or more additional peripheral buses form portions of a typical computer system.
A peripheral bus is formed, for instance, of an SCSI bus, an Extension to Industry Standard Architecture (EISA) bus, an Industry Standard Architecture (ISA) bus, or a Peripheral Component Interface (PCI) bus. The peripheral bus forms a communication path to and from a peripheral device connected thereto. The computer system CPU, or a plurality of CPUs in a multi-processor system, communicates with a computer peripheral device by way of a computer bus, such as one or more of the computer buses noted above.
A computer peripheral, depending upon its data transfer speed requirements, is connected to an appropriate peripheral bus, typically by way of a bus bridge that detects required actions, arbitrates, and translates both data and addresses between the various buses.
A computer peripheral device forming a portion of a single computer system might well be supplied by a manufacturer other than the manufacturer of the computer CPU. If the computer system contains more than one peripheral device, the peripheral devices might also be supplied by different manufacturers. Furthermore, the computer system may be operable pursuant to any of several different operating systems. The various combinations of computer peripheral devices and computer operating systems of which a computer system might be formed quickly becomes quite large.
Software drivers are typically required for each computer peripheral device to effectuate its operation. A software driver must be specifically tailored to operate in conjunction with the particular operating system operating on the computer. A multiplicity of software drivers might have to be created for a single computer peripheral to ensure that a computer peripheral device is operable together with any of the different operating systems.
The complexity resulting from such a requirement has led, at least in part, to the development of an Intelligent Input/Output (I
2
O) standard specification. The I
2
O standard specification sets forth, inter alia, standards for an I/O device driver architecture that is independent of both the specific peripheral device being controlled and the operating system of the computer system to which the device driver is to be installed.
In the I
2
O standard specification, the portion of the driver that is responsible for managing the peripheral device is logically separated from the specific implementation details of the operating system with which is to be installed. Because of this, the part of the driver that manages the peripheral device is portable across different computer and operating systems. The I
2
O standard specification also generalizes the nature of communication between the host computer system and peripheral hardware; thus, providing processor and bus technology independence.
Regardless of which bus protocol is deployed in a computer system or whether the computer system is I
2
O compliant, devices frequently employ bus master/slave functionality to communicate across a computer system bus. In a typical bus transaction, a single bus master sends information, including, but not limited to, address, data and control information to a single target device operating as a slave during a single bus transaction. In certain situations, however, it is desirable to broadcast the information to multiple targets. For example, in a fault—tolerant environment it is desirable to perform fast backup of data such as by providing mirrored disk drives. Conventional methods for broadcasting information to multiple targets requires moving the information multiple times using multiple bus transactions.
It would be advantageous therefore, to devise a method and apparatus which would effectuate low-latency distribution of data to multiple devices. It would further be advantageous if such a method and apparatus provided multicasting on a computer system bus wherein information from a single bus master is broadcast to multiple targets during a single bus transaction.
SUMMARY OF THE INVENTION
The present invention comprises a method and apparatus for broadcasting data to multiple target devices during a single bus transaction. Each of a plurality of potential target devices detect the beginning of a primary bus transaction and retrieve transaction command and target device identification information from a multicast bus. The transaction command information and target device identification information are decoded. A determination is made by each device as to whether the decoded target device identification information matches the identity of the device and furthermore whether the decoded transaction command is a read command. If the target device identification information matches the identity of the device and the command is a read, the device writes data present on the primary device into the device.
REFERENCES:
patent: 5829033 (1998-10-01), Hagersten et al.
patent: 5862148 (1999-01-01), Typaldos et al.
patent: 6052151 (2000-04-01), Tanaka
Mendel, Brett; “Server I/O all set to flow”;Lantimes, Oct. 27, 1997, vol. 14, Issue 22; cover page and p. 31.
Briggs, Chris; “Smarter and Faster I/O for Servers”; CORE: Operating Systems;Byte, May 1, 1996, vol. 2, No. 5.
Thompson, Tom; “I2O Beats I/O Bottlenecks”;Byte, Aug. 1997, pp. 85, 86 and 3 additional pages.
I2O Introduction; Technology Backgrounder; Aug. 13, 1997; http://www.i2osig.org/Architecture/TechBack.html.
i960®RP I/O Processor—the I2O SIG site; http://134.134.214.1/design/iio/i2osig.html; Feb. 6, 1998.
“Welcome to the I2O SIG® Web Site!”; http://www.i2osig.org; Feb. 6, 1998.
“About I2O Technology”; http://www.i2osig.org/Architecture; Feb. 6, 1998.
“Technology Backgrounder”; http://www.i2org/Architecture/TechBack.html; Feb. 6, 1998; 6 pages.
“Questions and Answers”; http://www.i2osig.org/Architecture/QandA.html; Feb. 6, 1998; 4 pages.
“I2O® Specifications For Non-Members”; http://www.i2osig.org/Architecture/GetSpec.html; Feb. 6, 1998.
Amdahl, Carlton G.; “I2O Future Directions”; http://www.i2osig.org; Jun. 1996; 12 pages.
Goble, Scott, et al.; “Intelligent I/O Architecture”; http://www.i2osig.org; Jun. 1996; 22 pages.
“
Bonola Thomas J.
Olarig Sompong P.
Compaq Computer Corp.
Etienne Ario
Fletcher Yoder & Van Someren
LandOfFree
Method and apparatus for multicasting on a bus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for multicasting on a bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for multicasting on a bus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2513987